[PATCH] D118160: [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: asb, luismarques, frasercrmck, khchen, arcbbb, kito-cheng.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, armkevincheng, eric-k256, StephenFan, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, kristof.beyls, mgorny.
Herald added a reviewer: sjarus.
craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

Using AArch64's original implementation for reference, this patch
implements a pass to remove unneeded copies of X0. This pass runs
after register allocation and looks to see if a register is implied
to be 0 by a branch in the predecessor basic block.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118160

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

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