[PATCH] D117764: [AArch64][SelectionDAG] CodeGen for Armv8.8/9.3 MOPS

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks. LGTM



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:939
 
-  // In case of strict alignment, avoid an excessive number of byte wide stores.
   MaxStoresPerMemsetOptSize = 8;
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Comment at: llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp:70
+    const EVT ResultTys[] = {MVT::i64, MVT::i64, MVT::Other};
+    MachineSDNode *Node = DAG.getMachineNode(MachineOpcode, DL, ResultTys, Ops);
+    DAG.setNodeMemRefs(Node, {DstOp});
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tyb0807 wrote:
> dmgreen wrote:
> > This is also creating Machine nodes very early. It may be better to create an ISD node for it instead. (Although I'm not sure how much it will matter - if there are no dag optimizations that happen for the memcpy nodes).
> Since we are not aware of any DAGCombine pattern allowing to optimize memcpy nodes, I propose to create Machine nodes here instead of defining new ISD nodes for these instructions, then do the ISD nodes -> Machine nodes somewhere else. What do you think?
It can cause issues here and there. But if we need it, we can change it later.


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https://reviews.llvm.org/D117764