[PATCH] D117546: [RISCV] Add patterns for vector widening floating-point fused multiply-add instructions

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan updated this revision to Diff 402791.
jacquesguan added a comment.

Add half->float test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117546/new/

https://reviews.llvm.org/D117546

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vfwmacc-sdnode.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D117546.402791.patch
Type: text/x-patch
Size: 75854 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220125/1952d4de/attachment.bin>