[llvm] aa50b93 - [AMDGPU][GlobalISel] Add more sign/zero/any-extension tests

Jay Foad via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 24 02:27:23 PST 2022 

Author: Jay Foad
Date: 2022-01-24T10:16:51Z
New Revision: aa50b93e7cf926dec5dd69920e6f48906ea8ad25

URL: https://github.com/llvm/llvm-project/commit/aa50b93e7cf926dec5dd69920e6f48906ea8ad25
DIFF: https://github.com/llvm/llvm-project/commit/aa50b93e7cf926dec5dd69920e6f48906ea8ad25.diff

LOG: [AMDGPU][GlobalISel] Add more sign/zero/any-extension tests

Add s1 to s16 cases, and for sgprs s1 to s64 and s32 to s64.

Added: 
    

Modified: 
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
    llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
index 3ae9735d11b9..cde4df501dfe 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
@@ -129,6 +129,26 @@ body:             |
 
 ---
 
+name: anyext_sgpr_s1_to_sgpr_s16
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s16
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[COPY]], 1048576, implicit-def $scc
+    ; GCN-NEXT: $sgpr0 = COPY [[S_BFE_U32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s1) = G_TRUNC %0
+    %2:sgpr(s16) = G_ANYEXT %1
+    %3:sgpr(s32) = G_ZEXT %2
+    $sgpr0 = COPY %3
+...
+
+---
+
 name: anyext_sgpr_s1_to_sgpr_s32
 legalized:       true
 regBankSelected: true
@@ -147,6 +167,46 @@ body: |
 
 ---
 
+name: anyext_sgpr_s1_to_sgpr_s64
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+    ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s1) = G_TRUNC %0
+    %2:sgpr(s64) = G_ANYEXT %1
+    $sgpr0_sgpr1 = COPY %2
+...
+
+---
+
+name: anyext_vgpr_s1_to_vgpr_s16
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: anyext_vgpr_s1_to_vgpr_s16
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[COPY]], 0, 16, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_U32_e64_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s1) = G_TRUNC %0
+    %2:vgpr(s16) = G_ANYEXT %1
+    %3:vgpr(s32) = G_ZEXT %2
+    $vgpr0 = COPY %3
+...
+
+---
+
 name: anyext_vgpr_s1_to_vgpr_s32
 legalized:       true
 regBankSelected: true

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
index ef7be3f7cd4a..0e7e12f27f71 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
@@ -3,6 +3,27 @@
 
 ---
 
+name: sext_sgpr_s1_to_sgpr_s16
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: sext_sgpr_s1_to_sgpr_s16
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32 = S_BFE_I32 [[COPY]], 65536, implicit-def $scc
+    ; GCN-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32 = S_BFE_U32 [[S_BFE_I32_]], 1048576, implicit-def $scc
+    ; GCN-NEXT: $sgpr0 = COPY [[S_BFE_U32_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s1) = G_TRUNC %0
+    %2:sgpr(s16) = G_SEXT %1
+    %3:sgpr(s32) = G_ZEXT %2
+    $sgpr0 = COPY %3
+...
+
+---
+
 name: sext_sgpr_s1_to_sgpr_s32
 legalized:       true
 regBankSelected: true
@@ -83,6 +104,27 @@ body: |
 
 ...
 
+---
+
+name: sext_sgpr_s32_to_sgpr_s64
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: sext_sgpr_s32_to_sgpr_s64
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+    ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[REG_SEQUENCE]], 2097152, implicit-def $scc
+    ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_I64_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s64) = G_SEXT %0
+    $sgpr0_sgpr1 = COPY %1
+
+...
+
 # ---
 
 # name: sext_vcc_s1_to_vgpr_s32
@@ -100,6 +142,27 @@ body: |
 
 ---
 
+name: sext_vgpr_s1_to_vgpr_s16
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: sext_vgpr_s1_to_vgpr_s16
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[COPY]], 0, 1, implicit $exec
+    ; GCN-NEXT: [[V_BFE_U32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_U32_e64 [[V_BFE_I32_e64_]], 0, 16, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_U32_e64_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s1) = G_TRUNC %0
+    %2:vgpr(s16) = G_SEXT %1
+    %3:vgpr(s32) = G_ZEXT %2
+    $vgpr0 = COPY %3
+...
+
+---
+
 name: sext_vgpr_s1_to_vgpr_s32
 legalized:       true
 regBankSelected: true

diff  --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
index c8d846868976..821d05f1f03a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
@@ -3,6 +3,27 @@
 
 ---
 
+name: zext_sgpr_s1_to_sgpr_s16
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: zext_sgpr_s1_to_sgpr_s16
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY]], 1, implicit-def $scc
+    ; GCN-NEXT: [[S_SEXT_I32_I16_:%[0-9]+]]:sreg_32 = S_SEXT_I32_I16 [[S_AND_B32_]]
+    ; GCN-NEXT: $sgpr0 = COPY [[S_SEXT_I32_I16_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s1) = G_TRUNC %0
+    %2:sgpr(s16) = G_ZEXT %1
+    %3:sgpr(s32) = G_SEXT %2
+    $sgpr0 = COPY %3
+...
+
+---
+
 name: zext_sgpr_s1_to_sgpr_s32
 legalized:       true
 regBankSelected: true
@@ -83,6 +104,27 @@ body: |
 
 ...
 
+---
+
+name: zext_sgpr_s32_to_sgpr_s64
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: zext_sgpr_s32_to_sgpr_s64
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
+    ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[REG_SEQUENCE]], 2097152, implicit-def $scc
+    ; GCN-NEXT: $sgpr0_sgpr1 = COPY [[S_BFE_U64_]]
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s64) = G_ZEXT %0
+    $sgpr0_sgpr1 = COPY %1
+
+...
+
 # ---
 
 # name: zext_vcc_s1_to_vgpr_s32
@@ -100,6 +142,27 @@ body: |
 
 ---
 
+name: zext_vgpr_s1_to_vgpr_s16
+legalized:       true
+regBankSelected: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: zext_vgpr_s1_to_vgpr_s16
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
+    ; GCN-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[V_AND_B32_e32_]], 0, 16, implicit $exec
+    ; GCN-NEXT: $vgpr0 = COPY [[V_BFE_I32_e64_]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s1) = G_TRUNC %0
+    %2:vgpr(s16) = G_ZEXT %1
+    %3:vgpr(s32) = G_SEXT %2
+    $vgpr0 = COPY %3
+...
+
+---
+
 name: zext_vgpr_s1_to_vgpr_s32
 legalized:       true
 regBankSelected: true

More information about the llvm-commits mailing list