[PATCH] D117803: [PowerPC] Update handling of splat loads for v4i32/v4f32/v2i64 to require non-extending loads.
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 21 05:21:34 PST 2022
nemanjai added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9102
+ LoadSDNode *LN = cast<LoadSDNode>(Op.getOperand(0));
+ if (!LN)
----------------
Can you move this up and change to `dyn_cast`? Then we should be able to simplify the early exit to something like
```
if (!LN || !Subtarget.hasVSX() || !ISD::isUNINDEXEDLoad(LN))
return false;
```
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:9115
+ // For v8i16 and v16i8 types, extending loads can be handled as long as the
+ // memory VT width is the same vector element VT type.
+ if ((Ty == MVT::v8i16 || Ty == MVT::v16i8) && ISD::isEXTLoad(InputNode) &&
----------------
Please add a note that the load will be an extending load because scalar `i8/i16` are not legal types.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D117803/new/
https://reviews.llvm.org/D117803
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