[PATCH] D117803: [PowerPC] Update handling of splat loads for v4i32/v4f32/v2i64 to require non-extending loads.

Thu Jan 20 09:45:23 PST 2022

amyk created this revision.
amyk added reviewers: PowerPC, shchenz, nemanjai.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: jeroen.dobbelaere, kosarev, kbarton, hiraditya.
amyk requested review of this revision.

This patch updates how splat loads handled and is an extension of D106555 <https://reviews.llvm.org/D106555>.

Particularly, for v2i64/v4f32/v4i32 types, they are updated to handle only non-extending loads.
For v8i16/v16i8 types, they are updated to handle extending loads only if the memory VT width is
the same vector element VT type.

A test case has been added to illustrate a scenario where a `PPCISD::LD_SPLAT` node should not
be produced. In this test, it depicts the following f64 extending load used in a v2f64 build vector, but
the extending load is actually used in more places other than the build vector (such as in `t12` and `t16`).

  Type-legalized selection DAG: %bb.0 'test:entry'
  SelectionDAG has 20 nodes:
    t0: ch = EntryToken
    t4: i64,ch = CopyFromReg t0, Register:i64 %1
    t6: i64,ch = CopyFromReg t0, Register:i64 %2
    t11: f64,ch = load<(load (s64) from %ir.b, !tbaa !7)> t0, t4, undef:i64
          t16: f64 = fadd t31, t37
        t34: ch = store<(store (s64) into %ir.c, !tbaa !7)> t31:1, t16, t6, undef:i64
      t36: ch = TokenFactor t34, t37:1
      t27: v2f64 = BUILD_VECTOR t37, t37
    t22: ch,glue = CopyToReg t36, Register:v2f64 $v2, t27
        t12: f64 = fadd t11, t37
      t28: ch = store<(store (s64) into %ir.b, !tbaa !7)> t11:1, t12, t4, undef:i64
    t31: f64,ch = load<(load (s64) from %ir.c, !tbaa !7)> t28, t6, undef:i64
      t2: i64,ch = CopyFromReg t0, Register:i64 %0
    t37: f64,ch = load<(load (s32) from %ir.a, !tbaa !3), anyext from f32> t0, t2, undef:i64
    t23: ch = PPCISD::RET_FLAG t22, Register:v2f64 $v2, t22:1

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117803

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/load-and-splat.ll

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