[PATCH] D117851: [Hexagon] Use llvm::Register instead of unsigned in HexagonConstExtenders.cpp. NFC.

[Jim Lin via Phabricator via llvm-commits]

Jim created this revision.
Herald added a subscriber: hiraditya.
Jim requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117851

Files:
  llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp


Index: llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -229,7 +229,7 @@
   private:
     struct Register {
       Register() = default;
-      Register(unsigned R, unsigned S) : Reg(R), Sub(S) {}
+      Register(llvm::Register R, unsigned S) : Reg(R), Sub(S) {}
       Register(const MachineOperand &Op)
         : Reg(Op.getReg()), Sub(Op.getSubReg()) {}
       Register &operator=(const MachineOperand &Op) {
@@ -1573,7 +1573,7 @@
         // No compounds are available. It is not clear whether we should
         // even process such extenders where the initializer cannot be
         // a single instruction, but do it for now.
-        unsigned TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
+        llvm::Register TmpR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
         BuildMI(MBB, At, dl, HII->get(Hexagon::S2_asl_i_r), TmpR)
           .add(MachineOperand(Ex.Rs))
           .addImm(Ex.S);


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D117851.401852.patch
Type: text/x-patch
Size: 1111 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220121/eda3f97c/attachment.bin>