[PATCH] D117573: [AArch64] Add patterns for relaxed atomic ld/st into fp registers

Thu Jan 20 11:44:17 PST 2022

danilaml added a comment.

In D117573#3258469 <https://reviews.llvm.org/D117573#3258469>, @samparker wrote:

> You mention unimplemented hooks in D60394 <https://reviews.llvm.org/D60394> and on the github issue, so why did you go for this approach instead? Solving this in a generic manner seems like the 'good' thing to do, no?

I didn't get an answer there and when I tried to prototype the hooks solution, I've noticed that atomic_load_N (and store) apparently is integer-only, so just to match fp AtomicLoads for correct lowering more stuff had to be introduced and it wouldn't really reduce the td boilerplate (just simplify it a bit). Maybe there is a better approach (actually, I wonder why "LD + MOV/MOV+ ST are not folded by some generic MIR pass), but I've decided to submit this targeted patch first.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117573/new/

https://reviews.llvm.org/D117573