[PATCH] D117574: [AArch64][SVE] POC: Use predicate registers for <N x i1> expression trees.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
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By default fixed-width i1 vectors are promoted, but when SVE is available,
some expression trees can be rewritten to use <vscale x M x i1> types,
such that all operations are performed on predicate registers, thus
avoiding unnecessary sign-extends and truncates.

The example chosen in this patch is to optimise an OR reduction
of a <N x i1> type, which can be implemented directly with a PTEST
instruction.

Note: this patch also contains a few other improvements that can be
split out into individual patches.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117574

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-ptest.ll

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