[PATCH] D117762: [AMDGPU] Set MemoryVT for truncstores in tblgen.
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 20 02:46:01 PST 2022
foad accepted this revision.
foad added a comment.
This revision is now accepted and ready to land.
LGTM. It would be nice to improve the codegen as noted inline but I'm not sure how to implement that.
================
Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll:268
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX10-NEXT: v_lshrrev_b16 v6, 8, v1
----------------
Now the only use of v5 is in `v_lshrrev_b16 v1, 8, v5` below, so we really ought to fold that somehow.
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rG LLVM Github Monorepo
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https://reviews.llvm.org/D117762/new/
https://reviews.llvm.org/D117762
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