[PATCH] D117561: [RISCV][VP] Lower VP_MERGE to RVV instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1085
 
+class VPseudoTiedBinaryCarryIn<VReg RetClass,
+                               VReg Op1Class,
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craig.topper wrote:
> Does it really need to tied or can we have a _TU instruction and pass the false value to two operands in the pattern match?
Let me rephrase that. We obviously need an operand that is tied. But it doesn't need to be the same as $rs2. We can assign $rs2 and the merge operand to the same src in the pattern.

But I guess we don't have the concept of _TU instructions until https://reviews.llvm.org/D117647


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117561/new/

https://reviews.llvm.org/D117561