[PATCH] D117561: [RISCV][VP] Lower VP_MERGE to RVV instructions
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 19 15:50:15 PST 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:253
+ // Vector select with a tied operand and additional VL operand. This
+ // operation is unmasked.
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Say which operand is tied
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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:255
+ // operation is unmasked.
+ VMERGE_VL,
// Vector select with an additional VL operand. This operation is unmasked.
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This is an unfortunate name collision with the RVV instruction. While also having weird constraints. Maybe VPMERGE_VL or VP_MERGE_VL would be slightly better?
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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td:1085
+class VPseudoTiedBinaryCarryIn<VReg RetClass,
+ VReg Op1Class,
----------------
Does it really need to tied or can we have a _TU instruction and pass the false value to two operands in the pattern match?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D117561/new/
https://reviews.llvm.org/D117561
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