[PATCH] D117689: [AArch64][SVE] Fold vselect into predicated fmul

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm added a reviewer: kmclaughlin.
peterwaller-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:501-518
+  multiclass vselect_to_pred_inst<SDPatternOperator Op, string Inst, ValueType Ty, ValueType PredTy> {
+    def : Pat<(vselect (PredTy PPR:$Pg), (Ty ZPR:$Zn), (Ty (Op (PredTy (AArch64ptrue 31)), (Ty ZPR:$Zn), (Ty ZPR:$Zm)))),
+              (!cast<Instruction>(Inst) PPR:$Pg, ZPR:$Zn, ZPR:$Zm)>;
+}
+
+  defm : vselect_to_pred_inst<AArch64fmul_p, "FMUL_ZPmZ_H", nxv8f16, nxv8i1>;
+  defm : vselect_to_pred_inst<AArch64fmul_p, "FMUL_ZPmZ_S", nxv4f32, nxv4i1>;
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You might be able to condense it to something like this suggestion, by introducing another multiclass in InstrFormats `SVE_VSelect_3_Op_Pat`, analogous to `SVE_3_Op_Pat_SelZero`. What you have looks reasonable to me, you might want a second opinion from someone else as to whether my proposal here makes sense.


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Comment at: llvm/test/CodeGen/AArch64/sve-fp-vselect.ll:89
+; CHECK-NEXT:    ret
+    %mul = fsub <vscale x 2 x double> %a, %b
+    %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %mul
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Register called `%mul` for an fsub -- looks like a few register names need updating.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117689/new/

https://reviews.llvm.org/D117689