[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rv32zbt-intrinsic.ll:21
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    fsr a0, a1, a0, a2
+; RV32ZBT-NEXT:    ret
----------------
This should have the same register order as the fsl test case. I think the test just needs to be re-generated.


================
Comment at: llvm/test/CodeGen/RISCV/rv32zbt-intrinsic.ll:27
+
+define i32 @fsri_i32(i32 %a, i32 %b) nounwind {
+; RV32ZBT-LABEL: fsri_i32:
----------------
Please add an fsli test case using llvm.riscv.fsl.i32 and a constant shift amount


================
Comment at: llvm/test/CodeGen/RISCV/rv32zbt-intrinsic.ll:30
+; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    fsri a0, a1, a0, 5
+; RV32ZBT-NEXT:    ret
----------------
This should be fsri a0, a0, a1, 5


================
Comment at: llvm/test/CodeGen/RISCV/rv64zbt-intrinsic.ll:27
+
+define i32 @fsri_i32(i32 %a, i32 %b) nounwind {
+; RV32ZBT-LABEL: fsri_i32:
----------------
Please add an fsli test case.


================
Comment at: llvm/test/CodeGen/RISCV/rv64zbt-intrinsic.ll:58
+
+define i64 @fsri_i64(i64 %a, i64 %b) nounwind {
+; RV32ZBT-LABEL: fsri_i64:
----------------
Please add a fsri test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117468/new/

https://reviews.llvm.org/D117468