[PATCH] D117468: [RISCV] Add intrinsic for Zbt extension

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng added a comment.

In D117468#3253493 <https://reviews.llvm.org/D117468#3253493>, @craig.topper wrote:

> Out of curiosity, what is your interest in Zbt? Do you work for a company that is implementing this extension in hardware?

My company has not implementing this extension，but may be in the future. I'm just doing a pre-research.



================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4246
+  case Intrinsic::riscv_fsl:
+    return DAG.getNode(RISCVISD::FSL, DL, XLenVT, Op.getOperand(1),
+                       Op.getOperand(2), Op.getOperand(3));
----------------
craig.topper wrote:
> craig.topper wrote:
> > craig.topper wrote:
> > > The operand order for RISCVISD::FSL/FSR match llvm.fshl and llvm.fshr rather than rs1, rs2, rs3 order. I think the operand order you want for riscv.fsl and riscv.fsr should be rs1, rs2, rs3.
> > > 
> > > And the assembly printing for fsl/fsr prints $rd, $rs1, $rs3, $rs2 makes this even more confusing.
> > > 
> > > I'll put up a patch to change RISCVISD::FSL/FSR and RISCVISD::FSLW/FSRW order to be in rs1, rs2, rs3 order.
> > i just noticed the proposed intrinsic order here https://github.com/riscv/riscv-bitmanip/blob/main-history/cproofs/rvintrin.h  uses rs1, rs3, rs2/shamt ordering. Which is different than the order used in the spec pseudo code. But rs1, rs3, rs2/shamt matches how the instructions are printed.
> > 
> > So I guess we should use rs1, rs3, rs2/shamt order. I'll update the RISCVISD opcodes accordingly.
> I pushed a patch to change the operand order of RISCVISD::FSL/FSR
I think change swap op2 and op3 in Pat, so shall i keep the order op1, op2, op3 here?

def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2),
          (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
def : Pat<(riscv_fsr GPR:$rs1, GPR:$rs3, GPR:$rs2),
          (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;


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https://reviews.llvm.org/D117468