[llvm] 9f27941 - [RISCV] Add patterns for vector narrowing integer right shift instructions
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 18 22:30:18 PST 2022
Author: eopXD
Date: 2022-01-18T22:30:13-08:00
New Revision: 9f27941c2fbb9ab032dde554b323e91793452625
URL: https://github.com/llvm/llvm-project/commit/9f27941c2fbb9ab032dde554b323e91793452625
DIFF: https://github.com/llvm/llvm-project/commit/9f27941c2fbb9ab032dde554b323e91793452625.diff
LOG: [RISCV] Add patterns for vector narrowing integer right shift instructions
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117454
Added:
llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 0f7db335a0904..9f34be6b7b2ce 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -602,6 +602,47 @@ multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> {
}
}
+multiclass VPatBinarySDNodeExt_V_WV<SDNode op, PatFrags extop, string instruction_name> {
+ foreach vti = AllWidenableIntVectors in {
+ def : Pat<
+ (vti.Vti.Vector
+ (riscv_trunc_vector_vl
+ (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+ (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
+ (riscv_vmset_vl VLMax),
+ VLMax)),
+ (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
+ vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
+ vti.Vti.AVL, vti.Vti.Log2SEW)>;
+ }
+}
+
+multiclass VPatBinarySDNodeExt_V_WX<SDNode op, PatFrags extop, string instruction_name> {
+ foreach vti = AllWidenableIntVectors in {
+ def : Pat<
+ (vti.Vti.Vector
+ (riscv_trunc_vector_vl
+ (op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
+ (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
+ (riscv_vmset_vl VLMax),
+ VLMax)),
+ (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX)
+ vti.Wti.RegClass:$rs2, GPR:$rs1,
+ vti.Vti.AVL, vti.Vti.Log2SEW)>;
+ }
+}
+
+
+multiclass VPatBinarySDNode_V_WV<SDNode op, string instruction_name> {
+ defm : VPatBinarySDNodeExt_V_WV<op, sext_oneuse, instruction_name>;
+ defm : VPatBinarySDNodeExt_V_WV<op, zext_oneuse, instruction_name>;
+}
+
+multiclass VPatBinarySDNode_V_WX<SDNode op, string instruction_name> {
+ defm : VPatBinarySDNodeExt_V_WX<op, sext_oneuse, instruction_name>;
+ defm : VPatBinarySDNodeExt_V_WX<op, zext_oneuse, instruction_name>;
+}
+
//===----------------------------------------------------------------------===//
// Patterns.
//===----------------------------------------------------------------------===//
@@ -696,6 +737,11 @@ foreach vti = AllIntegerVectors in {
}
// 12.7. Vector Narrowing Integer Right Shift Instructions
+defm : VPatBinarySDNode_V_WV<srl, "PseudoVNSRL">;
+defm : VPatBinarySDNode_V_WX<srl, "PseudoVNSRL">;
+defm : VPatBinarySDNode_V_WV<sra, "PseudoVNSRA">;
+defm : VPatBinarySDNode_V_WX<sra, "PseudoVNSRA">;
+
foreach vtiTowti = AllWidenableIntVectors in {
defvar vti = vtiTowti.Vti;
defvar wti = vtiTowti.Wti;
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
new file mode 100644
index 0000000000000..88d790c99b778
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll
@@ -0,0 +1,225 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsra.wv v8, v8, v9
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %x = ashr <vscale x 1 x i64> %va, %vc
+ %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv1i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsra.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+ %x = ashr <vscale x 1 x i64> %va, %vb
+ %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsra_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv2i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsra.wv v11, v8, v10
+; CHECK-NEXT: vmv.v.v v8, v11
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %x = ashr <vscale x 2 x i64> %va, %vc
+ %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv2i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsra.wx v10, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %x = ashr <vscale x 2 x i64> %va, %vb
+ %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsra_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv4i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsra.wv v14, v8, v12
+; CHECK-NEXT: vmv.v.v v8, v14
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %x = ashr <vscale x 4 x i64> %va, %vc
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv4i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsra.wx v12, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %x = ashr <vscale x 4 x i64> %va, %vb
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsra_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv8i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsra.wv v20, v8, v16
+; CHECK-NEXT: vmv.v.v v8, v20
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %x = ashr <vscale x 8 x i64> %va, %vc
+ %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv8i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsra.wx v16, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+ %x = ashr <vscale x 8 x i64> %va, %vb
+ %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsra_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv1i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsra.wv v8, v8, v9
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %x = ashr <vscale x 1 x i64> %va, %vc
+ %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsra_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv1i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsra.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+ %x = ashr <vscale x 1 x i64> %va, %vb
+ %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsra_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv2i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsra.wv v11, v8, v10
+; CHECK-NEXT: vmv.v.v v8, v11
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %x = ashr <vscale x 2 x i64> %va, %vc
+ %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsra_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv2i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsra.wx v10, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %x = ashr <vscale x 2 x i64> %va, %vb
+ %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsra_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv4i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsra.wv v14, v8, v12
+; CHECK-NEXT: vmv.v.v v8, v14
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %x = ashr <vscale x 4 x i64> %va, %vc
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsra_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv4i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsra.wx v12, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %x = ashr <vscale x 4 x i64> %va, %vb
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsra_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vnsra_wv_nxv8i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsra.wv v20, v8, v16
+; CHECK-NEXT: vmv.v.v v8, v20
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %x = ashr <vscale x 8 x i64> %va, %vc
+ %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsra_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsra_wx_i32_nxv8i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsra.wx v16, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+ %x = ashr <vscale x 8 x i64> %va, %vb
+ %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %y
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
new file mode 100644
index 0000000000000..fe243983f4ef2
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
@@ -0,0 +1,225 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -target-abi=ilp32 \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -target-abi=lp64 \
+; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
+
+define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv1i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %x = lshr <vscale x 1 x i64> %va, %vc
+ %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_sext(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+ %x = lshr <vscale x 1 x i64> %va, %vb
+ %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_sext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv2i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsrl.wv v11, v8, v10
+; CHECK-NEXT: vmv.v.v v8, v11
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %x = lshr <vscale x 2 x i64> %va, %vc
+ %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_sext(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %x = lshr <vscale x 2 x i64> %va, %vb
+ %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_sext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv4i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsrl.wv v14, v8, v12
+; CHECK-NEXT: vmv.v.v v8, v14
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %x = lshr <vscale x 4 x i64> %va, %vc
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_sext(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsrl.wx v12, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %x = lshr <vscale x 4 x i64> %va, %vb
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_sext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv8i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsrl.wv v20, v8, v16
+; CHECK-NEXT: vmv.v.v v8, v20
+; CHECK-NEXT: ret
+ %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %x = lshr <vscale x 8 x i64> %va, %vc
+ %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_sext(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsrl.wx v16, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+ %x = lshr <vscale x 8 x i64> %va, %vb
+ %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_zext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv1i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsrl.wv v8, v8, v9
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+ %x = lshr <vscale x 1 x i64> %va, %vc
+ %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 1 x i32> @vnsrl_wx_i32_nxv1i32_zext(<vscale x 1 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv1i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT: vnsrl.wx v8, v8, a0
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 1 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+ %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
+ %x = lshr <vscale x 1 x i64> %va, %vb
+ %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
+ ret <vscale x 1 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsrl_wv_nxv2i32_zext(<vscale x 2 x i64> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv2i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsrl.wv v11, v8, v10
+; CHECK-NEXT: vmv.v.v v8, v11
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+ %x = lshr <vscale x 2 x i64> %va, %vc
+ %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 2 x i32> @vnsrl_wx_i32_nxv2i32_zext(<vscale x 2 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv2i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT: vnsrl.wx v10, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v10
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 2 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+ %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
+ %x = lshr <vscale x 2 x i64> %va, %vb
+ %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
+ ret <vscale x 2 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsrl_wv_nxv4i32_zext(<vscale x 4 x i64> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv4i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsrl.wv v14, v8, v12
+; CHECK-NEXT: vmv.v.v v8, v14
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+ %x = lshr <vscale x 4 x i64> %va, %vc
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 4 x i32> @vnsrl_wx_i32_nxv4i32_zext(<vscale x 4 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv4i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT: vnsrl.wx v12, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v12
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 4 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+ %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
+ %x = lshr <vscale x 4 x i64> %va, %vb
+ %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
+ ret <vscale x 4 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsrl_wv_nxv8i32_zext(<vscale x 8 x i64> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vnsrl_wv_nxv8i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsrl.wv v20, v8, v16
+; CHECK-NEXT: vmv.v.v v8, v20
+; CHECK-NEXT: ret
+ %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+ %x = lshr <vscale x 8 x i64> %va, %vc
+ %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %y
+}
+
+define <vscale x 8 x i32> @vnsrl_wx_i32_nxv8i32_zext(<vscale x 8 x i64> %va, i32 %b) {
+; CHECK-LABEL: vnsrl_wx_i32_nxv8i32_zext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT: vnsrl.wx v16, v8, a0
+; CHECK-NEXT: vmv.v.v v8, v16
+; CHECK-NEXT: ret
+ %head = insertelement <vscale x 8 x i32> undef, i32 %b, i32 0
+ %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+ %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
+ %x = lshr <vscale x 8 x i64> %va, %vb
+ %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
+ ret <vscale x 8 x i32> %y
+}
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