[PATCH] D116743: [PowerPC] Add assembly comments for instructions that use the vector registers.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp updated this revision to Diff 400954.
stefanp added a comment.

Updated a whole set of tests that now have additional comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116743/new/

https://reviews.llvm.org/D116743

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstComments.h
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
  llvm/test/CodeGen/PowerPC/CSR-fit.ll
  llvm/test/CodeGen/PowerPC/aix-framepointer-save-restore.ll
  llvm/test/CodeGen/PowerPC/aix-p9-insert-extract.ll
  llvm/test/CodeGen/PowerPC/constant-pool.ll
  llvm/test/CodeGen/PowerPC/csr-save-restore-order.ll
  llvm/test/CodeGen/PowerPC/f128-aggregates.ll
  llvm/test/CodeGen/PowerPC/f128-compare.ll
  llvm/test/CodeGen/PowerPC/f128-fma.ll
  llvm/test/CodeGen/PowerPC/f128-passByValue.ll
  llvm/test/CodeGen/PowerPC/fminnum.ll
  llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
  llvm/test/CodeGen/PowerPC/fp-strict-round.ll
  llvm/test/CodeGen/PowerPC/frem.ll
  llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
  llvm/test/CodeGen/PowerPC/inline-asm-vsx-clobbers.ll
  llvm/test/CodeGen/PowerPC/larger-than-red-zone.ll
  llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
  llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
  llvm/test/CodeGen/PowerPC/p9-vinsert-vextract.ll
  llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
  llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
  llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
  llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
  llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll
  llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/PowerPC/pr48519.ll
  llvm/test/CodeGen/PowerPC/reg-scavenging.ll
  llvm/test/CodeGen/PowerPC/spill-vec-pair.ll
  llvm/test/CodeGen/PowerPC/vec-bswap.ll
  llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
  llvm/test/CodeGen/PowerPC/vector-reduce-fadd.ll
  llvm/test/CodeGen/PowerPC/vsx.ll