[PATCH] D117465: [RISCV] Add patterns to MIR sign-extension removal pass.
Mohammed Nurul Hoque via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 18 04:17:43 PST 2022
mohammed-nurulhoque updated this revision to Diff 400808.
mohammed-nurulhoque added a comment.
Thank you for your feedback. I fixed these errors now.
In the comment about DIV, by saying `(long)0x8000 0000`, I meant `0xffff fffff 8000 0000` which is a valid counter-example.
It turns out REMU doesn't work if only the dividend is sign-extended as you pointed out, but it propagates the sign-extension if both arguments are sign-extended.
I verified REM and REMU using https://alive2.llvm.org/ce/ with the following snippets. (Used i8/i16 instead of i32/i64 because it would time out otherwise, but it's the same principle).
REM:
define i16 @src(i8 %arg1, i16 %arg2) nounwind {
%1 = sext i8 %arg1 to i16
%2 = srem i16 %1, %arg2
%3 = trunc i16 %2 to i8
%4 = sext i8 %3 to i16
ret i16 %4
}
define i16 @tgt(i8 %arg1, i16 %arg2) nounwind {
%1 = sext i8 %arg1 to i16
%2 = srem i16 %1, %arg2
ret i16 %2
}
REMU:
define i16 @src(i8 %arg1, i8 %arg2) nounwind {
%1 = sext i8 %arg1 to i16
%2 = sext i8 %arg2 to i16
%3 = urem i16 %1, %2
%4 = trunc i16 %3 to i8
%5 = sext i8 %4 to i16
ret i16 %5
}
define i16 @tgt(i8 %arg1, i8 %arg2) nounwind {
%1 = sext i8 %arg1 to i16
%2 = sext i8 %arg2 to i16
%3 = urem i16 %1, %2
ret i16 %3
}
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D117465/new/
https://reviews.llvm.org/D117465
Files:
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
llvm/test/CodeGen/RISCV/sextw-removal.ll
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