[PATCH] D117465: [RISCV] Add patterns to MIR sign-extension removal pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp:176
+      // 32-bit, then so do Q & R. Sign-division doesn't work because of
+      // the edge case (long)0x8000 0000 / (long)-1
       // Logical operations use a sign extended 12-bit immediate. We just need
----------------
SDIV doesn't work, but not for the reason cited. If the dividend has 32 sign bits, then it isn't INT64_MIN so the overflow case of INT64_MIN/-1 can't happen.

The reason it doesn't work is because the SDIV instruction returns -2^63 for division by 0. That only has 1 sign bit. Division by 0 isn't undefined behavior at the MI level since the instruction has a definition.


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  https://reviews.llvm.org/D117465/new/

https://reviews.llvm.org/D117465