[PATCH] D117554: [SelDag] Fix incorrect assertion after 545624973628dfca.
Florian Hahn via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 18 03:43:47 PST 2022
fhahn created this revision.
Herald added a subscriber: hiraditya.
fhahn requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
This is an attempt to fix the failing pre-commit tests.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D117554
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -4407,10 +4407,12 @@
assert(getTypeAction(Mask.getValueType()) ==
TargetLowering::TypeWidenVector &&
"Unable to widen binary VP op");
+ EVT WideMaskVT =
+ TLI.getTypeToTransformTo(*DAG.getContext(), Mask.getValueType());
+ (void)WideMaskVT;
Mask = GetWidenedVector(Mask);
assert(Mask.getValueType().getVectorElementCount() ==
- TLI.getTypeToTransformTo(*DAG.getContext(), Mask.getValueType())
- .getVectorElementCount() &&
+ WideMaskVT.getVectorElementCount() &&
"Unable to widen vector load");
SDValue Res =
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