[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[Zakk Chen via Phabricator via llvm-commits]

khchen added a comment.

1. please add a check here <https://github.com/llvm/llvm-project/blob/c29d6c410e769938ed5db1090a1b894cf6061a4e/llvm/lib/Support/RISCVISAInfo.cpp#L704> and a clang cc1 test for it.
2. Have you try to run llvm-test-suite with rv32e config on qemu?



================
Comment at: llvm/lib/Support/TargetParser.cpp:339
+    if (ISAInfo.hasExtension("d"))
+      return "ilp32d";
     return "ilp32";
----------------
why do we need to change the order?


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  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D70401/new/

https://reviews.llvm.org/D70401