[PATCH] D117497: [X86] Add some missing dependency-breaking zero idiom patterns to scheduler models

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: pengfei, craig.topper, lebedev.ri, andreadb.
Herald added subscribers: gbedwell, hiraditya.
RKSimon requested review of this revision.
Herald added a project: LLVM.

Many of the x86 scheduler models are not accounting for their microarch's ability to handle dependency-breaking zero idioms (pxor xmm0,xmm0 etc.), which is causing some notable differences when comparing llvm-mca reports to iaca, uops.info etc.

These are based on the Intel AoMs and Agner's docs which list the instructions handled on each cpu model - there may be more, although tbh the xor/pxor/xorps/xorpd are by far the most commonly encountered.

Once this is in place we also need to review missing support for 'allones' idioms and reg-reg move elimination, but this needs fixing first.

@lebedev.ri The Barcelona test changes are due to the cpu still being tagged as using the SandyBridge model, if/when you get back to D63628 <https://reviews.llvm.org/D63628> these will need to be addressed.

Based on an original patch by @andreadb (Andrea Di Biagio)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117497

Files:
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedIceLake.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/lib/Target/X86/X86ScheduleSLM.td
  llvm/lib/Target/X86/X86ScheduleZnver1.td
  llvm/lib/Target/X86/X86ScheduleZnver2.td
  llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-1.s
  llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-2.s
  llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-3.s
  llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-4.s
  llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-5.s
  llvm/test/tools/llvm-mca/X86/Barcelona/reg-move-elimination-6.s
  llvm/test/tools/llvm-mca/X86/Barcelona/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/Broadwell/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/Haswell/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/IceLakeServer/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/SLM/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/SandyBridge/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/SkylakeClient/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/SkylakeServer/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/Znver1/zero-idioms.s
  llvm/test/tools/llvm-mca/X86/Znver2/zero-idioms.s

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