[PATCH] D114405: Optimize shift and accumulate pattern in AArch64.

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1800-1802
+    KnownBits Known2, Known3;
+    Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
+    Known3 = DAG.computeKnownBits(Op->getOperand(2), Depth + 1);
----------------
We don't appear to use Known2 and Known3


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Comment at: llvm/test/CodeGen/AArch64/shift-accumulate.ll:30
+
+define dso_local <2 x i64> @usra_v2i64(<4 x i32> %0) {
+; CHECK-LABEL: usra_v2i64:
----------------
Can you add the <1 x i64> version of this test (and ssra_v2i64 too). It should then test the "scalar" instructions with "d0" and "d1" operands.
You can remove dso_local too.



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114405/new/

https://reviews.llvm.org/D114405