[PATCH] D117947: [RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll:1
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
----------------
craig.topper wrote:
> eopXD wrote:
> > craig.topper wrote:
> > > Can we do this without splitting the tests back into rv32/rv64 versions?
> > > 
> > > Why do we need need `UTC_ARGS: --force-update`
> > > Can we do this without splitting the tests back into rv32/rv64 versions?
> > 
> > I looked into the test case. Looks like under rv64 and V it loads the argument using two instructions (one to load `%hi` and one to load `%lo`). I tried specifying TargetABI `lp64` for it but it didn't change. 
> > 
> > https://pastebin.com/vrkajMSN
> > 
> > What argument should I add to eliminate this situation? My understanding is that the differences are in XLEN (`rv32` vs `rv64`) and extensions (`zve` vs `v`). The machine instruction generated should only differ between different XLEN.
> It can't be fixed. There aren't enough bits in the GPR for RV32. We'll just need to have multiple check-prefixes. Something like
> 
> CHECK,RV32,RV32-ZVE32
> CHECK,RV32,RV32-V
> CHECK,RV64,RV64-ZVE32
> CHECK,RV64,RV64-V
Okay. I will do that and have a single file for an instruction.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117947/new/

https://reviews.llvm.org/D117947