[PATCH] D117947: [RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:919
 
-        setOperationAction(ISD::MULHS, VT, Custom);
-        setOperationAction(ISD::MULHU, VT, Custom);
+        // nxvXi64 MULHS/MULHU requires the V extension instead of Zve64*.
+        if (VT.getVectorElementType() != MVT::i64 ||
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This one should say vXi64. This is the fixed vector section.


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Comment at: llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll:1
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
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Can we do this without splitting the tests back into rv32/rv64 versions?

Why do we need need `UTC_ARGS: --force-update`


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D117947/new/

https://reviews.llvm.org/D117947