[PATCH] D117947: [RISCV] Don't allow i64 vector div by constant to use mulh with Zve64x

Yueh-Ting Chen via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Jan 22 00:47:10 PST 2022


eopXD created this revision.
eopXD added reviewers: craig.topper, asb, frasercrmck, kito-cheng.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
eopXD requested review of this revision.
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Herald added a project: LLVM.

EEW=64 of mulh and its vairants requires V extension.

Authored by: Craig Topper <craig.topper at sifive.com> @craig.topper
Co-Authored by: Eop Chen <eop.chen at sifive.com> @eopXD


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117947

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll

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