[PATCH] D117365: [InstCombine] optimize icmp-ugt-ashr

Sat Jan 15 12:12:37 PST 2022

craig.topper added a comment.

In D117365#3245910 <https://reviews.llvm.org/D117365#3245910>, @lebedev.ri wrote:

> Could you post the general proof, not for a single constant?

I think this is the general proof. It requires less pre-conditions than the sgt case.

https://alive2.llvm.org/ce/z/tFAcZt

================
Comment at: lib/Transforms/InstCombine/InstCombineCompares.cpp:2253
       APInt ShiftedC = (C + 1).shl(ShAmtVal) - 1;
       if (!C.isMaxSignedValue() && !(C + 1).shl(ShAmtVal).isMinSignedValue() &&
           (ShiftedC + 1).ashr(ShAmtVal) == (C + 1))
----------------
I believe the !C.isMaxSignedValue() is an unneeded condition for the signed case. If C.isMaxSignedValue() is true then C+1 is 0x80 for i8. `(ShiftedC + 1).ashr(ShAmtVal) == (C + 1)` could only possibly be true when ShAmtVal is 0. 0x80 only has 1 sign bit, any other ShAmtVal would mean that (C+1) would have more than 1 sign bit.

I'm not suggesting we remove it in this patch. Just pointing it out for alive proof purposes.

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  https://reviews.llvm.org/D117365/new/

https://reviews.llvm.org/D117365