[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll:68
+; RV32-NEXT:    li a0, 7
+; RV32-NEXT:    sub a0, a0, a1
+; RV32-NEXT:    vmv.x.s a1, v8
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I don't think I understand what this subtract is doing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389