[PATCH] D117389: [RISCV] Improve extract_vector_elt for fixed mask registers.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Jan 15 11:46:22 PST 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:4112
+        } else {
+          WideEleVT = XLenVT;
+          WidenVecLen = Nums / XLenVT.getScalarSizeInBits();
----------------
This won't work with Zve32 on RV64. A vector XLen elements wouldn't be legal.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117389/new/

https://reviews.llvm.org/D117389



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