[PATCH] D104163: [RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:480
+  defvar suffix = vti.LMul.MX # "_COMMUTABLE";
+  def : Pat<(vti.Vector (add vti.RegClass:$rs2,
+                              (mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
----------------
eopXD wrote:
> I am not familiar with SD Patterns and the TableGen syntax, so I may be wrong. 
> 
> According to v-spec:
> 
> ```
> vmacc.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
> ```
> 
> Shouldn't `$rs1` be multiplying with `$rs2` here? 
> 
> 
Aren't these patterns for

```
vmadd.vv vd, vs1, vs2, vm # vd[i] = (vs1[i] * vd[i]) + vs2[i]
```


Repository:
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  https://reviews.llvm.org/D104163/new/

https://reviews.llvm.org/D104163