[PATCH] D104163: [RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.

[Yueh-Ting Chen via Phabricator via llvm-commits]

eopXD added inline comments.
Herald added subscribers: VincentWu, luke957.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td:480
+  defvar suffix = vti.LMul.MX # "_COMMUTABLE";
+  def : Pat<(vti.Vector (add vti.RegClass:$rs2,
+                              (mul_oneuse vti.RegClass:$rs1, vti.RegClass:$rd))),
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I am not familiar with SD Patterns and the TableGen syntax, so I may be wrong. 

According to v-spec:

```
vmacc.vv vd, vs1, vs2, vm    # vd[i] = +(vs1[i] * vs2[i]) + vd[i]
```

Shouldn't `$rs1` be multiplying with `$rs2` here? 




Repository:
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  https://reviews.llvm.org/D104163/new/

https://reviews.llvm.org/D104163