[PATCH] D117355: [PowerPC] Fix the undef virtual register reading failure for PPC backend trap optimization

[Victor Huang via Phabricator via llvm-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, amyk, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.

This patch adds the fix for undef virtual register reading failure when trap optimization is enabled.

Failure scenario as below:

1. In a machine basic block A, the definition of a virtual register MI was eliminated due to trap optimization (TRAP inserted before the MI)
2. The same virtual register is still used in another machine basic block B (dominated by A) will trigger undef vr reading failure

Idea of the fix

1. Detect and set all virtual register definition after the conditional trap to `IMPLICIT_DEF`
2. Remove all the other machine instructions after the conditional trap and change the terminator machine instruction to an unconditional trap


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117355

Files:
  llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
  llvm/test/CodeGen/PowerPC/mi-peephole-trap-opt-dominated-block.mir

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