[PATCH] D117079: [RISCV] Improve i64 splat vector lowering in RV32.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2229
+    if (LoC == HiC && Const && Const->getSExtValue() == RISCV::VLMaxSentinel) {
+      MVT InterVT = MVT::getVectorVT(MVT::i32, 2 * VT.getVectorMinNumElements(),
+                                     VT.isScalableVector());
----------------
Can this be `MVT::getVectorVT(MVT::i32, 2 * VT.getVectorElementCount())` as I wrote in my previous comment. If not please tell me why not.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117079/new/

https://reviews.llvm.org/D117079