[PATCH] D117166: [AArch64][GlobalISel] Optimize conjunctions of compares to conditional conmpares.

Jessica Paquette via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jan 12 16:09:19 PST 2022


paquette accepted this revision.
paquette added a comment.
This revision is now accepted and ready to land.

LGTM, just have minor nits



================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp:1330
+/// changeFPCCToAArch64CC - Convert an IR fp condition code to an AArch64 CC.
+static void changeFPCCToAArch64CC(CmpInst::Predicate CC,
+                                  AArch64CC::CondCode &CondCode,
----------------
should this be named like `changeFPCCToORAArch64CC` to match `changeFPCCToANDAArch64CC`?


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp:4799
+      // If we the result of the OR will be negated and we can naturally negate
+      // the leafs, then this sub-tree as a whole negates naturally.
+      CanNegate = WillNegate && CanNegateL && CanNegateR;
----------------



================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp:4868
+      CC = CmpInst::getInversePredicate(CC);
+    // We only handle integer compares for now.
+    if (isa<GICmp>(Cmp)) {
----------------
comment seems inaccurate considering the FP case is handled right below?


================
Comment at: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp:4987
+    return false;
+  auto CSel =
+      MIB.buildInstr(MRI.getType(SelI.getReg(0)).getSizeInBits() == 32
----------------
should this use `emitSelect`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117166/new/

https://reviews.llvm.org/D117166



More information about the llvm-commits mailing list