[llvm] de3808c - [X86][AVX2] Add SimplifyDemandedVectorElts handling for avx2 per element shifts

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-01-12T14:50:28Z
New Revision: de3808c8fc0e2f55188a9f22fccac8106f41e285

URL: https://github.com/llvm/llvm-project/commit/de3808c8fc0e2f55188a9f22fccac8106f41e285
DIFF: https://github.com/llvm/llvm-project/commit/de3808c8fc0e2f55188a9f22fccac8106f41e285.diff

LOG: [X86][AVX2] Add SimplifyDemandedVectorElts handling for avx2 per element shifts

Noticed while investigating how to improve funnel shift codegen

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 2f59b09ebd067..b95624e2f6550 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -40083,7 +40083,10 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
     break;
   }
   case X86ISD::VPSHA:
-  case X86ISD::VPSHL: {
+  case X86ISD::VPSHL:
+  case X86ISD::VSHLV:
+  case X86ISD::VSRLV:
+  case X86ISD::VSRAV: {
     APInt LHSUndef, LHSZero;
     APInt RHSUndef, RHSZero;
     SDValue LHS = Op.getOperand(0);

diff  --git a/llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll b/llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll
index c07da079f6ea0..1128411571e7b 100644
--- a/llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll
@@ -89,7 +89,6 @@ define <8 x i32> @test3_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
 define <2 x i64> @demandedelts_vpsllvd(<2 x i64> %a0, <2 x i64> %a1) {
 ; CHECK-LABEL: demandedelts_vpsllvd:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpbroadcastq %xmm0, %xmm0
 ; CHECK-NEXT:    vpsllvq %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vpbroadcastq %xmm0, %xmm0
 ; CHECK-NEXT:    retq
@@ -102,7 +101,6 @@ define <2 x i64> @demandedelts_vpsllvd(<2 x i64> %a0, <2 x i64> %a1) {
 define <4 x i32> @demandedelts_vpsravd(<4 x i32> %a0, <4 x i32> %a1) {
 ; CHECK-LABEL: demandedelts_vpsravd:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,1]
 ; CHECK-NEXT:    vpsravd %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vpbroadcastd %xmm0, %xmm0
 ; CHECK-NEXT:    retq
@@ -115,7 +113,6 @@ define <4 x i32> @demandedelts_vpsravd(<4 x i32> %a0, <4 x i32> %a1) {
 define <4 x i64> @demandedelts_vpsrlvq(<4 x i64> %a0, <4 x i64> %a1) {
 ; CHECK-LABEL: demandedelts_vpsrlvq:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vpbroadcastq %xmm1, %ymm1
 ; CHECK-NEXT:    vpsrlvq %ymm1, %ymm0, %ymm0
 ; CHECK-NEXT:    vpbroadcastq %xmm0, %ymm0
 ; CHECK-NEXT:    retq