[llvm] 0c8d30a - [X86][AVX2] Add tests for missing demanded elts handling for avx2 per element shifts

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-01-12T14:50:27Z
New Revision: 0c8d30a305212adc0b751d2653552c75f27003ff

URL: https://github.com/llvm/llvm-project/commit/0c8d30a305212adc0b751d2653552c75f27003ff
DIFF: https://github.com/llvm/llvm-project/commit/0c8d30a305212adc0b751d2653552c75f27003ff.diff

LOG: [X86][AVX2] Add tests for missing demanded elts handling for avx2 per element shifts

Noticed while investigating how to improve funnel shift codegen

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll b/llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll
index 672820d86c6d1..c07da079f6ea0 100644
--- a/llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll
+++ b/llvm/test/CodeGen/X86/combine-avx2-intrinsics.ll
@@ -3,6 +3,9 @@
 
 ; Verify that the backend correctly combines AVX2 builtin intrinsics.
 
+;
+; VPBLEND Identities
+;
 
 define <16 x i16> @test_x86_avx2_pblendw(<16 x i16> %a0) {
 ; CHECK-LABEL: test_x86_avx2_pblendw:
@@ -79,7 +82,61 @@ define <8 x i32> @test3_x86_avx2_pblendd_256(<8 x i32> %a0, <8 x i32> %a1) {
   ret <8 x i32> %res
 }
 
+;
+; Demanded Elts
+;
+
+define <2 x i64> @demandedelts_vpsllvd(<2 x i64> %a0, <2 x i64> %a1) {
+; CHECK-LABEL: demandedelts_vpsllvd:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpbroadcastq %xmm0, %xmm0
+; CHECK-NEXT:    vpsllvq %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpbroadcastq %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %shuffle = shufflevector <2 x i64> %a0, <2 x i64> undef, <2 x i32> zeroinitializer
+  %shift = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %shuffle, <2 x i64> %a1)
+  %res = shufflevector <2 x i64> %shift, <2 x i64> undef, <2 x i32> zeroinitializer
+  ret <2 x i64> %res
+}
+
+define <4 x i32> @demandedelts_vpsravd(<4 x i32> %a0, <4 x i32> %a1) {
+; CHECK-LABEL: demandedelts_vpsravd:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,1]
+; CHECK-NEXT:    vpsravd %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vpbroadcastd %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %shuffle = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 1>
+  %shift = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %shuffle, <4 x i32> %a1)
+  %res = shufflevector <4 x i32> %shift, <4 x i32> undef, <4 x i32> zeroinitializer
+  ret <4 x i32> %res
+}
+
+define <4 x i64> @demandedelts_vpsrlvq(<4 x i64> %a0, <4 x i64> %a1) {
+; CHECK-LABEL: demandedelts_vpsrlvq:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpbroadcastq %xmm1, %ymm1
+; CHECK-NEXT:    vpsrlvq %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vpbroadcastq %xmm0, %ymm0
+; CHECK-NEXT:    retq
+  %shuffle = shufflevector <4 x i64> %a1, <4 x i64> undef, <4 x i32> zeroinitializer
+  %shift = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> %a0, <4 x i64> %shuffle)
+  %result = shufflevector <4 x i64> %shift, <4 x i64> undef, <4 x i32> zeroinitializer
+  ret <4 x i64> %result
+}
+
 declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i32)
 declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i32)
 declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i32)
 
+declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) nounwind readnone
+declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) nounwind readnone
+declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) nounwind readnone
+declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
+declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
+declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
+declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
+declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone