[PATCH] D117079: [RISCV] Improve i64 splat vector lowering in RV32.
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 11 19:19:21 PST 2022
jacquesguan created this revision.
jacquesguan added reviewers: craig.topper, asb, luismarques, frasercrmck, HsiangKai, khchen, benshi001.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, evandro, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
jacquesguan requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.
We could use vmv.v.i/vmv.v.x whose eew is 32 to lower the i64 splat vector if the i64 constant scalar could be splitted into two same i32 scalar.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D117079
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
Index: llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
+++ llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
@@ -728,14 +728,8 @@
define <vscale x 1 x i64> @intrinsic_vmv.v.x_i_nxv1i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv1i64_vlmax:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: li a0, 3
-; CHECK-NEXT: sw a0, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v8, (a0), zero
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.v.x.nxv1i64(
@@ -748,14 +742,8 @@
define <vscale x 2 x i64> @intrinsic_vmv.v.x_i_nxv2i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv2i64_vlmax:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: li a0, 3
-; CHECK-NEXT: sw a0, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v8, (a0), zero
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.v.x.nxv2i64(
@@ -768,14 +756,8 @@
define <vscale x 4 x i64> @intrinsic_vmv.v.x_i_nxv4i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv4i64_vlmax:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: li a0, 3
-; CHECK-NEXT: sw a0, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v8, (a0), zero
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.v.x.nxv4i64(
@@ -788,14 +770,8 @@
define <vscale x 8 x i64> @intrinsic_vmv.v.x_i_nxv8i64_vlmax() nounwind {
; CHECK-LABEL: intrinsic_vmv.v.x_i_nxv8i64_vlmax:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi sp, sp, -16
-; CHECK-NEXT: li a0, 3
-; CHECK-NEXT: sw a0, 12(sp)
-; CHECK-NEXT: sw a0, 8(sp)
-; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
-; CHECK-NEXT: addi a0, sp, 8
-; CHECK-NEXT: vlse64.v v8, (a0), zero
-; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
+; CHECK-NEXT: vmv.v.i v8, 3
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.v.x.nxv8i64(
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2210,6 +2210,18 @@
// node in order to try and match RVV vector/scalar instructions.
if ((LoC >> 31) == HiC)
return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Lo, VL);
+
+ // If vl is equal to VLMax and Hi constant is equal to Lo, we could use
+ // vmv.v.x whose EEW = 32 to lower it.
+ auto *Const = dyn_cast<ConstantSDNode>(VL);
+ if (LoC == HiC && Const && Const->getSExtValue() == RISCV::VLMaxSentinel) {
+ auto InterVT =
+ MVT::getScalableVectorVT(MVT::i32, 2 * VT.getVectorNumElements());
+ // TODO: if vl <= min(VLMAX), we could also do this. But we could not
+ // access the subtarget here now.
+ auto InterVec = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterVT, Lo, VL);
+ return DAG.getNode(ISD::BITCAST, DL, VT, InterVec);
+ }
}
// Fall back to a stack store and stride x0 vector load.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D117079.399177.patch
Type: text/x-patch
Size: 3869 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220112/68a2c79a/attachment.bin>
More information about the llvm-commits
mailing list