[PATCH] D117006: Add custom lowering for SELECT_CC fp128 using xsmaxcqp

[Ting Wang via Phabricator via llvm-commits]

tingwang created this revision.
tingwang added reviewers: nemanjai, jsji, shchenz, PowerPC.
tingwang added a project: LLVM.
Herald added subscribers: kbarton, hiraditya.
tingwang requested review of this revision.
Herald added a subscriber: llvm-commits.

Power ISA 3.1 adds xsmaxcqp/xsmincqp for quad-precision type-c max/min selection, and this opens the opportunity to improve instruction selection on: llvm.maxnum.f128, llvm.minnum.f128, and select_cc ordered gt/lt and (don't care) gt/lt.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D117006

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/scalar-min-max-p10.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D117006.398889.patch
Type: text/x-patch
Size: 5814 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20220111/122f66d9/attachment.bin>