[PATCH] D116581: [Aarch64] Customer lowering of COPYSIGN to SIMD should check for NEON availability

[Akshay kumar S via Phabricator via llvm-commits]

akshaykumars614 updated this revision to Diff 398538.
akshaykumars614 added a comment.

@dmgreen , I have updated the run lines.
I am feeling difficult in finding example for adding f64/f32/f16 tests in the testcase. It will be helpful if you provide me with the example.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116581/new/

https://reviews.llvm.org/D116581

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/fcopysign.ll


Index: llvm/test/CodeGen/AArch64/fcopysign.ll
===================================================================
--- llvm/test/CodeGen/AArch64/fcopysign.ll
+++ llvm/test/CodeGen/AArch64/fcopysign.ll
@@ -1,5 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -o - %s | FileCheck %s
+; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
+; RUN: llc < %s -march=aarch64 -mattr -neon | FileCheck -check-prefix=CHECK-NONEON %s
 ; Check that selection dag legalization of fcopysign works in cases with
 ; different modes for the arguments.
 target triple = "aarch64--"
@@ -26,6 +28,22 @@
 ; CHECK-NEXT:    strb w8, [sp, #15]
 ; CHECK-NEXT:    ldr q0, [sp], #16
 ; CHECK-NEXT:    ret
+;
+; CHECK-NONEON-LABEL: copysign0:
+; CHECK-NONEON:       // %bb.0: // %entry
+; CHECK-NONEON-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NONEON-NEXT:    adrp x8, .LCPI0_0
+; CHECK-NONEON-NEXT:    ldr q0, [x8, :lo12:.LCPI0_0]
+; CHECK-NONEON-NEXT:    adrp x8, val_double
+; CHECK-NONEON-NEXT:    str q0, [sp, #-16]!
+; CHECK-NONEON-NEXT:    ldr x8, [x8, :lo12:val_double]
+; CHECK-NONEON-NEXT:    ldrb w9, [sp, #15]
+; CHECK-NONEON-NEXT:    and x8, x8, #0x8000000000000000
+; CHECK-NONEON-NEXT:    lsr x8, x8, #56
+; CHECK-NONEON-NEXT:    bfxil w8, w9, #0, #7
+; CHECK-NONEON-NEXT:    strb w8, [sp, #15]
+; CHECK-NONEON-NEXT:    ldr q0, [sp], #16
+; CHECK-NONEON-NEXT:    ret
 entry:
   %v = load double, double* @val_double, align 8
   %conv = fpext double %v to fp128
@@ -49,6 +67,22 @@
 ; CHECK-NEXT:    strb w8, [sp, #15]
 ; CHECK-NEXT:    ldr q0, [sp], #16
 ; CHECK-NEXT:    ret
+;
+; CHECK-NONEON-LABEL: copysign1:
+; CHECK-NONEON:       // %bb.0: // %entry
+; CHECK-NONEON-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NONEON-NEXT:    adrp x8, val_fp128
+; CHECK-NONEON-NEXT:    ldr q0, [x8, :lo12:val_fp128]
+; CHECK-NONEON-NEXT:    adrp x8, val_float
+; CHECK-NONEON-NEXT:    str q0, [sp, #-16]!
+; CHECK-NONEON-NEXT:    ldr w8, [x8, :lo12:val_float]
+; CHECK-NONEON-NEXT:    ldrb w9, [sp, #15]
+; CHECK-NONEON-NEXT:    and w8, w8, #0x80000000
+; CHECK-NONEON-NEXT:    lsr w8, w8, #24
+; CHECK-NONEON-NEXT:    bfxil w8, w9, #0, #7
+; CHECK-NONEON-NEXT:    strb w8, [sp, #15]
+; CHECK-NONEON-NEXT:    ldr q0, [sp], #16
+; CHECK-NONEON-NEXT:    ret
 entry:
   %v0 = load fp128, fp128* @val_fp128, align 16
   %v1 = load float, float* @val_float, align 4
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7256,6 +7256,8 @@
     return getSVESafeBitCast(VT, IntResult, DAG);
   }
 
+  if (!Subtarget->hasNEON())
+    return SDValue();
   if (SrcVT.bitsLT(VT))
     In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
   else if (SrcVT.bitsGT(VT))


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