[PATCH] D106237: [ISel] Port AArch64 HADD and RHADD to ISel

Fri Jan 7 13:30:36 PST 2022

craig.topper added a comment.

In D106237#3114240 <https://reviews.llvm.org/D106237#3114240>, @dmgreen wrote:

> In D106237#3112542 <https://reviews.llvm.org/D106237#3112542>, @craig.topper wrote:
>
>> Instead of making this part of SimplifyDemandedBits, could you emit (and (sext (hadds X, Y)), 0x7fffffff) for the (lshr (add (sext(X), sext(Y)), 1) case and let the AND be optimized by itself? Or would the transform not be profitable if it doesn't get removed?
>
> Yeah that might work. Like https://alive2.llvm.org/ce/z/9pwKEi. I'll have to check if it looks worse anywhere - I think it should be fine in general, possibly minus the cost of materializing the constant.

Did you check on this?

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https://reviews.llvm.org/D106237