[PATCH] D106237: [ISel] Port AArch64 HADD and RHADD to ISel
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 7 13:15:58 PST 2022
craig.topper added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:18379
!cast<ConstantSDNode>(Value)->isOpaque())) {
APInt TruncDemandedBits =
APInt::getLowBitsSet(Value.getScalarValueSizeInBits(),
----------------
This APInt goes with the code after this new code. Move it down?
================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:946
+ // - Needs 1 demanded bit zero and >= 2 sign bits.
+ unsigned NumSignedA = DAG.ComputeNumSignBits(ExtOpA);
+ unsigned NumSignedB = DAG.ComputeNumSignBits(ExtOpB);
----------------
This needs to forward the Depth from the caller.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:957
+ KnownBits = std::min(NumSignedA, NumSignedB) - 1;
+ } else if (NumZeroA >= 2 && NumZeroB >= 2) {
+ IsSigned = false;
----------------
ComputeNumSignBits can call computeKnownBits internally and will count leading 0s as sign bits. Does the zero check need to have priority here?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106237/new/
https://reviews.llvm.org/D106237
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