[llvm] 5476585 - [Hexagon] Improve check for subinstruction registers

[Krzysztof Parzyszek via llvm-commits]

Author: colinl
Date: 2022-01-07T11:33:14-08:00
New Revision: 547658567353d581bd6acbd5f3b3cdd94da2118e

URL: https://github.com/llvm/llvm-project/commit/547658567353d581bd6acbd5f3b3cdd94da2118e
DIFF: https://github.com/llvm/llvm-project/commit/547658567353d581bd6acbd5f3b3cdd94da2118e.diff

LOG: [Hexagon] Improve check for subinstruction registers

Added: 
    

Modified: 
    llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
index 33b2e9a9e302..d7c0f71cdac4 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
@@ -777,9 +777,13 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
   assert(!MO.isImm());
   if (MO.isReg()) {
     unsigned Reg = MO.getReg();
-    if (HexagonMCInstrInfo::isSubInstruction(MI) ||
-        HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ)
+    switch (HexagonMCInstrInfo::getDesc(MCII, MI).OpInfo[OperandNumber].RegClass) {
+    case GeneralSubRegsRegClassID:
+    case GeneralDoubleLow8RegsRegClassID:
       return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
+    default:
+      break;
+    }
     return MCT.getRegisterInfo()->getEncodingValue(Reg);
   }