[PATCH] D116749: [AArch64][SVE] Fold predicate into compare

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 398100.
c-rhodes added a comment.

Add test Dave suggested


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116749/new/

https://reviews.llvm.org/D116749

Files:
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll


Index: llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
@@ -963,6 +963,29 @@
   ret <vscale x 4 x i1> %out
 }
 
+; Verify general predicate is folded into the compare
+define <vscale x 4 x i1> @predicated_icmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
+; CHECK-LABEL: predicated_icmp:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT:    cmpge p0.s, p0/z, z2.s, z1.s
+; CHECK-NEXT:    ret
+  %icmp1 = icmp sgt <vscale x 4 x i32> %a, %b
+  %icmp2 = icmp sle <vscale x 4 x i32> %b, %c
+  %and = and <vscale x 4 x i1> %icmp1, %icmp2
+  ret <vscale x 4 x i1> %and
+}
+
+define <vscale x 4 x i1> @predicated_icmp_unknown_lhs(<vscale x 4 x i1> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
+; CHECK-LABEL: predicated_icmp_unknown_lhs:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, z0.s
+; CHECK-NEXT:    ret
+  %icmp = icmp sle <vscale x 4 x i32> %b, %c
+  %and = and <vscale x 4 x i1> %a, %icmp
+  ret <vscale x 4 x i1> %and
+}
 
 declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
 declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
Index: llvm/lib/Target/AArch64/SVEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -4641,6 +4641,10 @@
             (cmp $Op1, $Op2, $Op3)>;
   def : Pat<(predvt (AArch64setcc_z predvt:$Op1, intvt:$Op2, intvt:$Op3, invcc)),
             (cmp $Op1, $Op3, $Op2)>;
+  def : Pat<(predvt (and predvt:$Pg, (AArch64setcc_z (predvt (AArch64ptrue 31)), intvt:$Op2, intvt:$Op3, cc))),
+            (cmp $Pg, $Op2, $Op3)>;
+  def : Pat<(predvt (and predvt:$Pg, (AArch64setcc_z (predvt (AArch64ptrue 31)), intvt:$Op2, intvt:$Op3, invcc))),
+            (cmp $Pg, $Op3, $Op2)>;
 }
 
 multiclass SVE_SETCC_Pat_With_Zero<CondCode cc, CondCode invcc, ValueType predvt,


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