[PATCH] D116765: [x86] make select lowering using SBB hack more flexible

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:24565
       }
-
-      Cmp = DAG.getNode(X86ISD::SUB, DL, CmpVTs,
-                        CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
-
+      // TODO: Can this be undef? We don't need "0 - 0" here. We only need to
+      //       constrain the operands so any 1 register is used for both ops.
----------------
craig.topper wrote:
> Might be able to use X86ISD::SETCC_CARRY? Though SBB with identical source is only recognized as a special case on AMD CPUs last I knew.
Aha - I always forget that we have that node. Yes, we should be using that...something like this:
      SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
                         DAG.getTargetConstant(X86::COND_B, DL, MVT::i8),
                         Cmp.getValue(1));

That's going to cause a few more test diffs though, so I'd prefer to make it another patch.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116765/new/

https://reviews.llvm.org/D116765