[PATCH] D116799: [RISCV] Add precommit test for select vl op that equal to ~0.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan created this revision.
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Precommit test for D116798 <https://reviews.llvm.org/D116798>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D116799

Files:
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll


Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
+++ llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
@@ -239,6 +239,21 @@
   ret <vscale x 1 x double> %y
 }
 
+define <vscale x 1 x double> @test13(<vscale x 1 x double> %a, <vscale x 1 x double> %b) nounwind {
+; CHECK-LABEL: test13:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li a0, -1
+; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, mu
+; CHECK-NEXT:    vfadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
+entry:
+  %0 = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64(
+    <vscale x 1 x double> %a,
+    <vscale x 1 x double> %b,
+    i64 -1)
+  ret <vscale x 1 x double> %0
+}
+
 declare <vscale x 1 x i64> @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i64>,


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