[PATCH] D116421: [RISCV][LegalizeIntegerTypes] Teach PromoteSetCCOperands not to sext i32 comparisons for RV64 if the promoted values are already zero extended.

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jan 4 11:27:49 PST 2022


craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:1753
+  // inserting a zext_inreg operation that we might not be able to remove.
+  if (ISD::isIntEqualitySetCC(CCCode)) {
+    unsigned OpLEffectiveBits = DAG.ComputeMinSignedBits(OpL);
----------------
efriedma wrote:
> Do we need to check isIntEqualitySetCC here?  We can sign-extend the operands of unsigned comparisons if we want to.
We don't. I just did it due to lack of test coverage and not wanting to increase compile time unnecessarily. A lot of the tests that the equality case triggers on are from Arguments having "signext". I thought it might be unlikely for a signext operand to be used by an unsigned compare. But now that I think about it, InstCombine can turn "x >= 0 && x < 10" into "x u< 10."


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116421/new/

https://reviews.llvm.org/D116421



More information about the llvm-commits mailing list