[PATCH] D115594: [AVR] Optimize int16 shift operation for shift amount greater than 8

Ayke via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jan 3 13:14:13 PST 2022

Previous message: [PATCH] D116554: [VPlan] Add & use utility to check if only the first lane is used.
Next message: [PATCH] D115594: [AVR] Optimize int16 shift operation for shift amount greater than 8
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

aykevl added a comment.

Is there a reason why you introduced 3 new pseudo instructions? It seems to me that the existing 16-bit shift instructions (LSLWN, LSRWN, ASRWN) should already be able to support this.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115594/new/

https://reviews.llvm.org/D115594

Previous message: [PATCH] D116554: [VPlan] Add & use utility to check if only the first lane is used.
Next message: [PATCH] D115594: [AVR] Optimize int16 shift operation for shift amount greater than 8
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list