[llvm] fd48088 - [llvm] Remove redundant member initialization (NFC)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 3 10:03:22 PST 2022
This is causing lots of warnings from gcc on my machine. For example
*llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:* In copy
constructor ‘*{anonymous}::RISCVOperand::RISCVOperand(const
{anonymous}::RISCVOperand&)*’:
*llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:308:3:* *warning: *base
class ‘*class llvm::MCParsedAsmOperand*’ should be explicitly initialized
in the copy constructor [*-Wextra*]
*RISCVOperand*(const RISCVOperand &o) {
*^~~~~~~~~~~~*
~Craig
On Sat, Jan 1, 2022 at 4:18 PM Kazu Hirata via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
>
> Author: Kazu Hirata
> Date: 2022-01-01T16:18:18-08:00
> New Revision: fd4808887ee47f3ec8a030e9211169ef4fb094c3
>
> URL:
> https://github.com/llvm/llvm-project/commit/fd4808887ee47f3ec8a030e9211169ef4fb094c3
> DIFF:
> https://github.com/llvm/llvm-project/commit/fd4808887ee47f3ec8a030e9211169ef4fb094c3.diff
>
> LOG: [llvm] Remove redundant member initialization (NFC)
>
> Identified with readability-redundant-member-init.
>
> Added:
>
>
> Modified:
> llvm/include/llvm/ADT/Triple.h
> llvm/include/llvm/Analysis/BasicAliasAnalysis.h
> llvm/include/llvm/Analysis/DDG.h
> llvm/include/llvm/Analysis/LazyCallGraph.h
> llvm/include/llvm/Analysis/MemoryLocation.h
> llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h
> llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h
> llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
> llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
> llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
> llvm/include/llvm/CodeGen/MachinePassManager.h
> llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
> llvm/include/llvm/DWARFLinker/DWARFLinker.h
> llvm/include/llvm/DebugInfo/GSYM/StringTable.h
> llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
> llvm/include/llvm/FileCheck/FileCheck.h
> llvm/include/llvm/IR/LegacyPassManagers.h
> llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
> llvm/include/llvm/MCA/HardwareUnits/LSUnit.h
> llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
> llvm/include/llvm/MCA/Stages/EntryStage.h
> llvm/include/llvm/MCA/Stages/ExecuteStage.h
> llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
> llvm/include/llvm/MCA/Stages/InstructionTables.h
> llvm/include/llvm/MCA/Stages/RetireStage.h
> llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
> llvm/include/llvm/Remarks/RemarkSerializer.h
> llvm/include/llvm/Support/ScopedPrinter.h
> llvm/include/llvm/Transforms/IPO/Attributor.h
> llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
> llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp
> llvm/lib/Analysis/CallGraphSCCPass.cpp
> llvm/lib/Analysis/DDG.cpp
> llvm/lib/Analysis/GlobalsModRef.cpp
> llvm/lib/Analysis/IVUsers.cpp
> llvm/lib/Analysis/LoopCacheAnalysis.cpp
> llvm/lib/Analysis/LoopPass.cpp
> llvm/lib/Analysis/RegionPass.cpp
> llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
> llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
> llvm/lib/CodeGen/MIRParser/MIRParser.cpp
> llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
> llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
> llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
> llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp
> llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
> llvm/lib/IR/LegacyPassManager.cpp
> llvm/lib/IR/Module.cpp
> llvm/lib/InterfaceStub/IFSStub.cpp
> llvm/lib/MC/MCParser/AsmParser.cpp
> llvm/lib/MC/MCParser/MasmParser.cpp
> llvm/lib/MCA/Stages/DispatchStage.cpp
> llvm/lib/MCA/Stages/InOrderIssueStage.cpp
> llvm/lib/Remarks/BitstreamRemarkSerializer.cpp
> llvm/lib/Remarks/RemarkStreamer.cpp
> llvm/lib/Remarks/RemarkStringTable.cpp
> llvm/lib/Remarks/YAMLRemarkParser.cpp
> llvm/lib/Support/YAMLParser.cpp
> llvm/lib/Target/AArch64/AArch64Subtarget.cpp
> llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
> llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
> llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h
> llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
> llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
> llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
> llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
> llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
> llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
> llvm/lib/Target/ARM/ARMHazardRecognizer.h
> llvm/lib/Target/ARM/ARMInstrInfo.cpp
> llvm/lib/Target/ARM/ARMInstructionSelector.cpp
> llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
> llvm/lib/Target/ARM/ARMRegisterInfo.cpp
> llvm/lib/Target/ARM/ARMTargetObjectFile.h
> llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
> llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
> llvm/lib/Target/AVR/AVRSubtarget.cpp
> llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
> llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
> llvm/lib/Target/BPF/BPFSubtarget.cpp
> llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
> llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
> llvm/lib/Target/Lanai/LanaiSubtarget.cpp
> llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
> llvm/lib/Target/MSP430/MSP430Subtarget.cpp
> llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
> llvm/lib/Target/Mips/MipsInstructionSelector.cpp
> llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
> llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
> llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
> llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
> llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h
> llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
> llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
> llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
> llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
> llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
> llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
> llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
> llvm/lib/Target/Sparc/SparcTargetObjectFile.h
> llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
> llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
> llvm/lib/Target/VE/VEMachineFunctionInfo.h
> llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
> llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
> llvm/lib/Target/X86/X86InstructionSelector.cpp
> llvm/lib/Target/X86/X86RegisterBankInfo.cpp
> llvm/lib/Target/XCore/XCoreSubtarget.cpp
> llvm/lib/Transforms/IPO/Inliner.cpp
> llvm/lib/Transforms/IPO/PartialInlining.cpp
> llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
> llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
> llvm/lib/Transforms/Vectorize/VPlan.h
> llvm/tools/dsymutil/BinaryHolder.h
> llvm/tools/dsymutil/Reproducer.cpp
> llvm/tools/llvm-cov/CoverageSummaryInfo.h
> llvm/tools/llvm-mca/CodeRegion.h
> llvm/tools/llvm-mca/PipelinePrinter.h
> llvm/tools/llvm-objcopy/ELF/Object.h
> llvm/tools/llvm-objdump/SourcePrinter.h
> llvm/tools/llvm-profdata/llvm-profdata.cpp
> llvm/tools/llvm-readobj/llvm-readobj.cpp
> llvm/utils/TableGen/GlobalISel/GIMatchDag.h
> llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp
> llvm/utils/TableGen/GlobalISelEmitter.cpp
> llvm/utils/TableGen/PredicateExpander.h
> llvm/utils/TableGen/RegisterBankEmitter.cpp
>
> Removed:
>
>
>
>
> ################################################################################
> diff --git a/llvm/include/llvm/ADT/Triple.h
> b/llvm/include/llvm/ADT/Triple.h
> index 6f1f1618fbc27..45a8b8d927140 100644
> --- a/llvm/include/llvm/ADT/Triple.h
> +++ b/llvm/include/llvm/ADT/Triple.h
> @@ -271,9 +271,7 @@ class Triple {
>
> /// Default constructor is the same as an empty string and leaves all
> /// triple fields unknown.
> - Triple()
> - : Data(), Arch(), SubArch(), Vendor(), OS(), Environment(),
> - ObjectFormat() {}
> + Triple() : Arch(), SubArch(), Vendor(), OS(), Environment(),
> ObjectFormat() {}
>
> explicit Triple(const Twine &Str);
> Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine
> &OSStr);
>
> diff --git a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
> b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
> index ed9d1ba4c5a75..361765d852574 100644
> --- a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
> +++ b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h
> @@ -58,7 +58,7 @@ class BasicAAResult : public AAResultBase<BasicAAResult>
> {
> BasicAAResult(const DataLayout &DL, const Function &F,
> const TargetLibraryInfo &TLI, AssumptionCache &AC,
> DominatorTree *DT = nullptr, PhiValues *PV = nullptr)
> - : AAResultBase(), DL(DL), F(F), TLI(TLI), AC(AC), DT(DT), PV(PV) {}
> + : DL(DL), F(F), TLI(TLI), AC(AC), DT(DT), PV(PV) {}
>
> BasicAAResult(const BasicAAResult &Arg)
> : AAResultBase(Arg), DL(Arg.DL), F(Arg.F), TLI(Arg.TLI), AC(Arg.AC),
>
> diff --git a/llvm/include/llvm/Analysis/DDG.h
> b/llvm/include/llvm/Analysis/DDG.h
> index 51dd4a738f00b..4ea589ec7efc8 100644
> --- a/llvm/include/llvm/Analysis/DDG.h
> +++ b/llvm/include/llvm/Analysis/DDG.h
> @@ -52,7 +52,7 @@ class DDGNode : public DDGNodeBase {
> };
>
> DDGNode() = delete;
> - DDGNode(const NodeKind K) : DDGNodeBase(), Kind(K) {}
> + DDGNode(const NodeKind K) : Kind(K) {}
> DDGNode(const DDGNode &N) : DDGNodeBase(N), Kind(N.Kind) {}
> DDGNode(DDGNode &&N) : DDGNodeBase(std::move(N)), Kind(N.Kind) {}
> virtual ~DDGNode() = 0;
>
> diff --git a/llvm/include/llvm/Analysis/LazyCallGraph.h
> b/llvm/include/llvm/Analysis/LazyCallGraph.h
> index 0580f4d7b226c..5828274cc02bc 100644
> --- a/llvm/include/llvm/Analysis/LazyCallGraph.h
> +++ b/llvm/include/llvm/Analysis/LazyCallGraph.h
> @@ -1190,7 +1190,7 @@ class LazyCallGraph {
> }
> };
>
> -inline LazyCallGraph::Edge::Edge() : Value() {}
> +inline LazyCallGraph::Edge::Edge() {}
> inline LazyCallGraph::Edge::Edge(Node &N, Kind K) : Value(&N, K) {}
>
> inline LazyCallGraph::Edge::operator bool() const {
>
> diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h
> b/llvm/include/llvm/Analysis/MemoryLocation.h
> index 833fce1b17265..23e50f601e042 100644
> --- a/llvm/include/llvm/Analysis/MemoryLocation.h
> +++ b/llvm/include/llvm/Analysis/MemoryLocation.h
> @@ -284,8 +284,7 @@ class MemoryLocation {
> return T.isScalable() ? UnknownSize : T.getFixedSize();
> }
>
> - MemoryLocation()
> - : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()),
> AATags() {}
> + MemoryLocation() : Ptr(nullptr),
> Size(LocationSize::beforeOrAfterPointer()) {}
>
> explicit MemoryLocation(const Value *Ptr, LocationSize Size,
> const AAMDNodes &AATags = AAMDNodes())
>
> diff --git a/llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h
> b/llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h
> index b4f4e5f29768b..d19a6394bd486 100644
> --- a/llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h
> +++ b/llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h
> @@ -40,7 +40,7 @@ class ObjCARCAAResult : public
> AAResultBase<ObjCARCAAResult> {
> const DataLayout &DL;
>
> public:
> - explicit ObjCARCAAResult(const DataLayout &DL) : AAResultBase(), DL(DL)
> {}
> + explicit ObjCARCAAResult(const DataLayout &DL) : DL(DL) {}
> ObjCARCAAResult(ObjCARCAAResult &&Arg)
> : AAResultBase(std::move(Arg)), DL(Arg.DL) {}
>
>
> diff --git a/llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h
> b/llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h
> index 20acb407ead00..ebd427354cee9 100644
> --- a/llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h
> +++ b/llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h
> @@ -27,7 +27,7 @@ class SCEVAAResult : public AAResultBase<SCEVAAResult> {
> ScalarEvolution &SE;
>
> public:
> - explicit SCEVAAResult(ScalarEvolution &SE) : AAResultBase(), SE(SE) {}
> + explicit SCEVAAResult(ScalarEvolution &SE) : SE(SE) {}
> SCEVAAResult(SCEVAAResult &&Arg) : AAResultBase(std::move(Arg)),
> SE(Arg.SE) {}
>
> AliasResult alias(const MemoryLocation &LocA, const MemoryLocation
> &LocB,
>
> diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
> b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
> index 1fd07ca2c8d42..f6563971f9812 100644
> --- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
> +++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
> @@ -159,7 +159,7 @@ template <typename DerivedT> class CodeGenPassBuilder {
> class AddIRPass {
> public:
> AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true)
> - : MPM(MPM), FPM() {
> + : MPM(MPM) {
> if (Check)
> AddingFunctionPasses = false;
> }
>
> diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
> b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
> index 9c878d4b087ba..82c125993ec3d 100644
> --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
> +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
> @@ -95,7 +95,7 @@ class CallLowering {
> bool IsFixed = true)
> : ArgInfo(Regs, OrigValue.getType(), OrigIndex, Flags, IsFixed,
> &OrigValue) {}
>
> - ArgInfo() : BaseArgInfo() {}
> + ArgInfo() {}
> };
>
> struct CallLoweringInfo {
>
> diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
> b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
> index a02b15639946d..9507c3411b5c8 100644
> --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
> +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
> @@ -556,7 +556,7 @@ class LegalizeRuleSet {
> }
>
> public:
> - LegalizeRuleSet() : AliasOf(0), IsAliasedByAnother(false), Rules() {}
> + LegalizeRuleSet() : AliasOf(0), IsAliasedByAnother(false) {}
>
> bool isAliasedByAnother() { return IsAliasedByAnother; }
> void setIsAliasedByAnother() { IsAliasedByAnother = true; }
>
> diff --git a/llvm/include/llvm/CodeGen/MachinePassManager.h
> b/llvm/include/llvm/CodeGen/MachinePassManager.h
> index f967167c65e13..75b8a89c812e9 100644
> --- a/llvm/include/llvm/CodeGen/MachinePassManager.h
> +++ b/llvm/include/llvm/CodeGen/MachinePassManager.h
> @@ -40,10 +40,10 @@ class MachineFunctionAnalysisManager : public
> AnalysisManager<MachineFunction> {
> public:
> using Base = AnalysisManager<MachineFunction>;
>
> - MachineFunctionAnalysisManager() : Base(), FAM(nullptr), MAM(nullptr) {}
> + MachineFunctionAnalysisManager() : FAM(nullptr), MAM(nullptr) {}
> MachineFunctionAnalysisManager(FunctionAnalysisManager &FAM,
> ModuleAnalysisManager &MAM)
> - : Base(), FAM(&FAM), MAM(&MAM) {}
> + : FAM(&FAM), MAM(&MAM) {}
> MachineFunctionAnalysisManager(MachineFunctionAnalysisManager &&) =
> default;
> MachineFunctionAnalysisManager &
> operator=(MachineFunctionAnalysisManager &&) = default;
> @@ -135,7 +135,7 @@ class MachineFunctionPassManager
> MachineFunctionPassManager(bool DebugLogging = false,
> bool RequireCodeGenSCCOrder = false,
> bool VerifyMachineFunction = false)
> - : Base(), RequireCodeGenSCCOrder(RequireCodeGenSCCOrder),
> + : RequireCodeGenSCCOrder(RequireCodeGenSCCOrder),
> VerifyMachineFunction(VerifyMachineFunction) {}
> MachineFunctionPassManager(MachineFunctionPassManager &&) = default;
> MachineFunctionPassManager &
>
> diff --git a/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
> b/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
> index 6a3d76be0ed63..0f3af915da649 100644
> --- a/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
> +++ b/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h
> @@ -39,7 +39,7 @@ class BaseIndexOffset {
> public:
> BaseIndexOffset() = default;
> BaseIndexOffset(SDValue Base, SDValue Index, bool IsIndexSignExt)
> - : Base(Base), Index(Index), Offset(),
> IsIndexSignExt(IsIndexSignExt) {}
> + : Base(Base), Index(Index), IsIndexSignExt(IsIndexSignExt) {}
> BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
> bool IsIndexSignExt)
> : Base(Base), Index(Index), Offset(Offset),
>
> diff --git a/llvm/include/llvm/DWARFLinker/DWARFLinker.h
> b/llvm/include/llvm/DWARFLinker/DWARFLinker.h
> index 1c6d0b1ead86b..4f1c666df35fa 100644
> --- a/llvm/include/llvm/DWARFLinker/DWARFLinker.h
> +++ b/llvm/include/llvm/DWARFLinker/DWARFLinker.h
> @@ -385,8 +385,8 @@ class DWARFLinker {
> : Die(Die), Type(T), CU(CU), Flags(0), OtherInfo(OtherInfo) {}
>
> WorklistItem(unsigned AncestorIdx, CompileUnit &CU, unsigned Flags)
> - : Die(), Type(WorklistItemType::LookForParentDIEsToKeep), CU(CU),
> - Flags(Flags), AncestorIdx(AncestorIdx) {}
> + : Type(WorklistItemType::LookForParentDIEsToKeep), CU(CU),
> Flags(Flags),
> + AncestorIdx(AncestorIdx) {}
> };
>
> /// returns true if we need to translate strings.
>
> diff --git a/llvm/include/llvm/DebugInfo/GSYM/StringTable.h
> b/llvm/include/llvm/DebugInfo/GSYM/StringTable.h
> index 045c9e3f3ebd2..6dd90499c203a 100644
> --- a/llvm/include/llvm/DebugInfo/GSYM/StringTable.h
> +++ b/llvm/include/llvm/DebugInfo/GSYM/StringTable.h
> @@ -20,7 +20,7 @@ namespace gsym {
> /// string at offset zero. Strings must be UTF8 NULL terminated strings.
> struct StringTable {
> StringRef Data;
> - StringTable() : Data() {}
> + StringTable() {}
> StringTable(StringRef D) : Data(D) {}
> StringRef operator[](size_t Offset) const { return getString(Offset); }
> StringRef getString(uint32_t Offset) const {
>
> diff --git a/llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
> b/llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
> index 4bb11bf62593a..779dc885372d6 100644
> --- a/llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
> +++ b/llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h
> @@ -87,7 +87,7 @@ class PlainPrinterBase : public DIPrinter {
>
> public:
> PlainPrinterBase(raw_ostream &OS, raw_ostream &ES, PrinterConfig
> &Config)
> - : DIPrinter(), OS(OS), ES(ES), Config(Config) {}
> + : OS(OS), ES(ES), Config(Config) {}
>
> void print(const Request &Request, const DILineInfo &Info) override;
> void print(const Request &Request, const DIInliningInfo &Info) override;
> @@ -138,7 +138,7 @@ class JSONPrinter : public DIPrinter {
>
> public:
> JSONPrinter(raw_ostream &OS, PrinterConfig &Config)
> - : DIPrinter(), OS(OS), Config(Config) {}
> + : OS(OS), Config(Config) {}
>
> void print(const Request &Request, const DILineInfo &Info) override;
> void print(const Request &Request, const DIInliningInfo &Info) override;
>
> diff --git a/llvm/include/llvm/FileCheck/FileCheck.h
> b/llvm/include/llvm/FileCheck/FileCheck.h
> index 6ed75e14ccb65..7a6c98db3029b 100644
> --- a/llvm/include/llvm/FileCheck/FileCheck.h
> +++ b/llvm/include/llvm/FileCheck/FileCheck.h
> @@ -80,8 +80,7 @@ class FileCheckType {
> std::bitset<FileCheckKindModifier::Size> Modifiers;
>
> public:
> - FileCheckType(FileCheckKind Kind = CheckNone)
> - : Kind(Kind), Count(1), Modifiers() {}
> + FileCheckType(FileCheckKind Kind = CheckNone) : Kind(Kind), Count(1) {}
> FileCheckType(const FileCheckType &) = default;
> FileCheckType &operator=(const FileCheckType &) = default;
>
>
> diff --git a/llvm/include/llvm/IR/LegacyPassManagers.h
> b/llvm/include/llvm/IR/LegacyPassManagers.h
> index 0bcb408d49292..e161bdee961a4 100644
> --- a/llvm/include/llvm/IR/LegacyPassManagers.h
> +++ b/llvm/include/llvm/IR/LegacyPassManagers.h
> @@ -460,8 +460,7 @@ class PMDataManager {
> class FPPassManager : public ModulePass, public PMDataManager {
> public:
> static char ID;
> - explicit FPPassManager()
> - : ModulePass(ID), PMDataManager() { }
> + explicit FPPassManager() : ModulePass(ID) {}
>
> /// run - Execute all of the passes scheduled for execution. Keep
> track of
> /// whether any of the passes modifies the module, and if so, return
> true.
>
> diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
> b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
> index 908ee30e40609..2f57b85a92321 100644
> --- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
> +++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
> @@ -68,9 +68,7 @@ struct IntelExpr {
> StringRef OffsetName;
> unsigned Scale;
>
> - IntelExpr()
> - : NeedBracs(false), Imm(0), BaseReg(StringRef()),
> IndexReg(StringRef()),
> - OffsetName(StringRef()), Scale(1) {}
> + IntelExpr() : NeedBracs(false), Imm(0), Scale(1) {}
> // [BaseReg + IndexReg * ScaleExpression + OFFSET name +
> ImmediateExpression]
> IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale,
> StringRef offsetName, int64_t imm, bool needBracs)
>
> diff --git a/llvm/include/llvm/MCA/HardwareUnits/LSUnit.h
> b/llvm/include/llvm/MCA/HardwareUnits/LSUnit.h
> index 7eddd067aa0cc..c05f770df8ebe 100644
> --- a/llvm/include/llvm/MCA/HardwareUnits/LSUnit.h
> +++ b/llvm/include/llvm/MCA/HardwareUnits/LSUnit.h
> @@ -55,7 +55,7 @@ class MemoryGroup {
> MemoryGroup()
> : NumPredecessors(0), NumExecutingPredecessors(0),
> NumExecutedPredecessors(0), NumInstructions(0), NumExecuting(0),
> - NumExecuted(0), CriticalPredecessor(),
> CriticalMemoryInstruction() {}
> + NumExecuted(0), CriticalPredecessor() {}
> MemoryGroup(MemoryGroup &&) = default;
>
> size_t getNumSuccessors() const {
>
> diff --git a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
> b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
> index b679b0d7d5373..7467fd6754f0c 100644
> --- a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
> +++ b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
> @@ -118,8 +118,8 @@ class DefaultResourceStrategy final : public
> ResourceStrategy {
>
> public:
> DefaultResourceStrategy(uint64_t UnitMask)
> - : ResourceStrategy(), ResourceUnitMask(UnitMask),
> - NextInSequenceMask(UnitMask), RemovedFromNextInSequence(0) {}
> + : ResourceUnitMask(UnitMask), NextInSequenceMask(UnitMask),
> + RemovedFromNextInSequence(0) {}
> virtual ~DefaultResourceStrategy() = default;
>
> uint64_t select(uint64_t ReadyMask) override;
>
> diff --git a/llvm/include/llvm/MCA/Stages/EntryStage.h
> b/llvm/include/llvm/MCA/Stages/EntryStage.h
> index 1c133898d603e..4c50838bef4b1 100644
> --- a/llvm/include/llvm/MCA/Stages/EntryStage.h
> +++ b/llvm/include/llvm/MCA/Stages/EntryStage.h
> @@ -36,7 +36,7 @@ class EntryStage final : public Stage {
> EntryStage &operator=(const EntryStage &Other) = delete;
>
> public:
> - EntryStage(SourceMgr &SM) : CurrentInstruction(), SM(SM), NumRetired(0)
> { }
> + EntryStage(SourceMgr &SM) : SM(SM), NumRetired(0) {}
>
> bool isAvailable(const InstRef &IR) const override;
> bool hasWorkToComplete() const override;
>
> diff --git a/llvm/include/llvm/MCA/Stages/ExecuteStage.h
> b/llvm/include/llvm/MCA/Stages/ExecuteStage.h
> index 4c09ca8255ff6..03a78a8b6b85b 100644
> --- a/llvm/include/llvm/MCA/Stages/ExecuteStage.h
> +++ b/llvm/include/llvm/MCA/Stages/ExecuteStage.h
> @@ -49,7 +49,7 @@ class ExecuteStage final : public Stage {
> public:
> ExecuteStage(Scheduler &S) : ExecuteStage(S, false) {}
> ExecuteStage(Scheduler &S, bool ShouldPerformBottleneckAnalysis)
> - : Stage(), HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0),
> + : HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0),
> EnablePressureEvents(ShouldPerformBottleneckAnalysis) {}
>
> // This stage works under the assumption that the Pipeline will
> eventually
>
> diff --git a/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
> b/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
> index 42f386a13d85f..40bc3b5aed949 100644
> --- a/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
> +++ b/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h
> @@ -38,7 +38,7 @@ struct StallInfo {
> unsigned CyclesLeft;
> StallKind Kind;
>
> - StallInfo() : IR(), CyclesLeft(), Kind(StallKind::DEFAULT) {}
> + StallInfo() : CyclesLeft(), Kind(StallKind::DEFAULT) {}
>
> StallKind getStallKind() const { return Kind; }
> unsigned getCyclesLeft() const { return CyclesLeft; }
>
> diff --git a/llvm/include/llvm/MCA/Stages/InstructionTables.h
> b/llvm/include/llvm/MCA/Stages/InstructionTables.h
> index 35b21b0ba94d2..9617fd49db6e0 100644
> --- a/llvm/include/llvm/MCA/Stages/InstructionTables.h
> +++ b/llvm/include/llvm/MCA/Stages/InstructionTables.h
> @@ -32,7 +32,7 @@ class InstructionTables final : public Stage {
>
> public:
> InstructionTables(const MCSchedModel &Model)
> - : Stage(), SM(Model), Masks(Model.getNumProcResourceKinds()) {
> + : SM(Model), Masks(Model.getNumProcResourceKinds()) {
> computeProcResourceMasks(Model, Masks);
> }
>
>
> diff --git a/llvm/include/llvm/MCA/Stages/RetireStage.h
> b/llvm/include/llvm/MCA/Stages/RetireStage.h
> index b635a01db85e6..aafe2815df150 100644
> --- a/llvm/include/llvm/MCA/Stages/RetireStage.h
> +++ b/llvm/include/llvm/MCA/Stages/RetireStage.h
> @@ -36,7 +36,7 @@ class RetireStage final : public Stage {
>
> public:
> RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)
> - : Stage(), RCU(R), PRF(F), LSU(LS) {}
> + : RCU(R), PRF(F), LSU(LS) {}
>
> bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
> Error cycleStart() override;
>
> diff --git a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
> b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
> index d3a5d44ce8ddc..e1f45019b1a92 100644
> --- a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
> +++ b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
> @@ -702,7 +702,7 @@ class LineCoverageIterator
>
> LineCoverageIterator(const CoverageData &CD, unsigned Line)
> : CD(CD), WrappedSegment(nullptr), Next(CD.begin()), Ended(false),
> - Line(Line), Segments(), Stats() {
> + Line(Line) {
> this->operator++();
> }
>
>
> diff --git a/llvm/include/llvm/Remarks/RemarkSerializer.h
> b/llvm/include/llvm/Remarks/RemarkSerializer.h
> index 97fd224ea082d..90e556df87e78 100644
> --- a/llvm/include/llvm/Remarks/RemarkSerializer.h
> +++ b/llvm/include/llvm/Remarks/RemarkSerializer.h
> @@ -48,7 +48,7 @@ struct RemarkSerializer {
>
> RemarkSerializer(Format SerializerFormat, raw_ostream &OS,
> SerializerMode Mode)
> - : SerializerFormat(SerializerFormat), OS(OS), Mode(Mode), StrTab()
> {}
> + : SerializerFormat(SerializerFormat), OS(OS), Mode(Mode) {}
>
> /// This is just an interface.
> virtual ~RemarkSerializer() = default;
>
> diff --git a/llvm/include/llvm/Support/ScopedPrinter.h
> b/llvm/include/llvm/Support/ScopedPrinter.h
> index 865337e3cc7f5..803ae47793df0 100644
> --- a/llvm/include/llvm/Support/ScopedPrinter.h
> +++ b/llvm/include/llvm/Support/ScopedPrinter.h
> @@ -799,7 +799,7 @@ struct DelimitedScope {
> };
>
> struct DictScope : DelimitedScope {
> - explicit DictScope() : DelimitedScope() {}
> + explicit DictScope() {}
> explicit DictScope(ScopedPrinter &W) : DelimitedScope(W) {
> W.objectBegin(); }
>
> DictScope(ScopedPrinter &W, StringRef N) : DelimitedScope(W) {
> @@ -818,7 +818,7 @@ struct DictScope : DelimitedScope {
> };
>
> struct ListScope : DelimitedScope {
> - explicit ListScope() : DelimitedScope() {}
> + explicit ListScope() {}
> explicit ListScope(ScopedPrinter &W) : DelimitedScope(W) {
> W.arrayBegin(); }
>
> ListScope(ScopedPrinter &W, StringRef N) : DelimitedScope(W) {
>
> diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h
> b/llvm/include/llvm/Transforms/IPO/Attributor.h
> index 1a9dde03aabc6..233f1be04f56b 100644
> --- a/llvm/include/llvm/Transforms/IPO/Attributor.h
> +++ b/llvm/include/llvm/Transforms/IPO/Attributor.h
> @@ -2365,7 +2365,7 @@ struct BooleanState : public IntegerStateBase<bool,
> 1, 0> {
> using super = IntegerStateBase<bool, 1, 0>;
> using base_t = IntegerStateBase::base_t;
>
> - BooleanState() : super() {}
> + BooleanState() {}
> BooleanState(base_t Assumed) : super(Assumed) {}
>
> /// Set the assumed value to \p Value but never below the known one.
>
> diff --git a/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
> b/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
> index 419729271a236..7ba9d65cae55d 100644
> --- a/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
> +++ b/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
> @@ -435,8 +435,7 @@ class FunctionToLoopPassAdaptor
> bool UseBlockFrequencyInfo = false,
> bool UseBranchProbabilityInfo =
> false,
> bool LoopNestMode = false)
> - : Pass(std::move(Pass)), LoopCanonicalizationFPM(),
> - UseMemorySSA(UseMemorySSA),
> + : Pass(std::move(Pass)), UseMemorySSA(UseMemorySSA),
> UseBlockFrequencyInfo(UseBlockFrequencyInfo),
> UseBranchProbabilityInfo(UseBranchProbabilityInfo),
> LoopNestMode(LoopNestMode) {
>
> diff --git a/llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp
> b/llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp
> index 9467bb3c9b2dd..090dccc53b6ea 100644
> --- a/llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp
> +++ b/llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp
> @@ -63,7 +63,7 @@ using namespace llvm::cflaa;
>
> CFLSteensAAResult::CFLSteensAAResult(
> std::function<const TargetLibraryInfo &(Function &F)> GetTLI)
> - : AAResultBase(), GetTLI(std::move(GetTLI)) {}
> + : GetTLI(std::move(GetTLI)) {}
> CFLSteensAAResult::CFLSteensAAResult(CFLSteensAAResult &&Arg)
> : AAResultBase(std::move(Arg)), GetTLI(std::move(Arg.GetTLI)) {}
> CFLSteensAAResult::~CFLSteensAAResult() = default;
>
> diff --git a/llvm/lib/Analysis/CallGraphSCCPass.cpp
> b/llvm/lib/Analysis/CallGraphSCCPass.cpp
> index f2e5eab72bf28..930cb13c0cb30 100644
> --- a/llvm/lib/Analysis/CallGraphSCCPass.cpp
> +++ b/llvm/lib/Analysis/CallGraphSCCPass.cpp
> @@ -61,7 +61,7 @@ class CGPassManager : public ModulePass, public
> PMDataManager {
> public:
> static char ID;
>
> - explicit CGPassManager() : ModulePass(ID), PMDataManager() {}
> + explicit CGPassManager() : ModulePass(ID) {}
>
> /// Execute all of the passes scheduled for execution. Keep track of
> /// whether any of the passes modifies the module, and if so, return
> true.
>
> diff --git a/llvm/lib/Analysis/DDG.cpp b/llvm/lib/Analysis/DDG.cpp
> index da5de75a038cf..7e1357959a3f2 100644
> --- a/llvm/lib/Analysis/DDG.cpp
> +++ b/llvm/lib/Analysis/DDG.cpp
> @@ -106,7 +106,7 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const
> DDGNode &N) {
>
> //===--------------------------------------------------------------------===//
>
> SimpleDDGNode::SimpleDDGNode(Instruction &I)
> - : DDGNode(NodeKind::SingleInstruction), InstList() {
> + : DDGNode(NodeKind::SingleInstruction) {
> assert(InstList.empty() && "Expected empty list.");
> InstList.push_back(&I);
> }
>
> diff --git a/llvm/lib/Analysis/GlobalsModRef.cpp
> b/llvm/lib/Analysis/GlobalsModRef.cpp
> index d00a7c944f10a..53262d88ba51a 100644
> --- a/llvm/lib/Analysis/GlobalsModRef.cpp
> +++ b/llvm/lib/Analysis/GlobalsModRef.cpp
> @@ -102,7 +102,7 @@ class GlobalsAAResult::FunctionInfo {
> "Insufficient low bits to store our flag and ModRef
> info.");
>
> public:
> - FunctionInfo() : Info() {}
> + FunctionInfo() {}
> ~FunctionInfo() {
> delete Info.getPointer();
> }
> @@ -963,7 +963,7 @@ ModRefInfo GlobalsAAResult::getModRefInfo(const
> CallBase *Call,
> GlobalsAAResult::GlobalsAAResult(
> const DataLayout &DL,
> std::function<const TargetLibraryInfo &(Function &F)> GetTLI)
> - : AAResultBase(), DL(DL), GetTLI(std::move(GetTLI)) {}
> + : DL(DL), GetTLI(std::move(GetTLI)) {}
>
> GlobalsAAResult::GlobalsAAResult(GlobalsAAResult &&Arg)
> : AAResultBase(std::move(Arg)), DL(Arg.DL),
> GetTLI(std::move(Arg.GetTLI)),
>
> diff --git a/llvm/lib/Analysis/IVUsers.cpp b/llvm/lib/Analysis/IVUsers.cpp
> index d7b202f831890..0f3929f455062 100644
> --- a/llvm/lib/Analysis/IVUsers.cpp
> +++ b/llvm/lib/Analysis/IVUsers.cpp
> @@ -254,7 +254,7 @@ IVStrideUse &IVUsers::AddUser(Instruction *User, Value
> *Operand) {
>
> IVUsers::IVUsers(Loop *L, AssumptionCache *AC, LoopInfo *LI,
> DominatorTree *DT,
> ScalarEvolution *SE)
> - : L(L), AC(AC), LI(LI), DT(DT), SE(SE), IVUses() {
> + : L(L), AC(AC), LI(LI), DT(DT), SE(SE) {
> // Collect ephemeral values so that AddUsersIfInteresting skips them.
> EphValues.clear();
> CodeMetrics::collectEphemeralValues(L, AC, EphValues);
>
> diff --git a/llvm/lib/Analysis/LoopCacheAnalysis.cpp
> b/llvm/lib/Analysis/LoopCacheAnalysis.cpp
> index 7b895d8a5dc2a..ba014bd08c987 100644
> --- a/llvm/lib/Analysis/LoopCacheAnalysis.cpp
> +++ b/llvm/lib/Analysis/LoopCacheAnalysis.cpp
> @@ -477,9 +477,8 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const
> CacheCost &CC) {
>
> CacheCost::CacheCost(const LoopVectorTy &Loops, const LoopInfo &LI,
> ScalarEvolution &SE, TargetTransformInfo &TTI,
> - AAResults &AA, DependenceInfo &DI,
> - Optional<unsigned> TRT)
> - : Loops(Loops), TripCounts(), LoopCosts(),
> + AAResults &AA, DependenceInfo &DI,
> Optional<unsigned> TRT)
> + : Loops(Loops),
> TRT((TRT == None) ? Optional<unsigned>(TemporalReuseThreshold) :
> TRT),
> LI(LI), SE(SE), TTI(TTI), AA(AA), DI(DI) {
> assert(!Loops.empty() && "Expecting a non-empty loop vector.");
>
> diff --git a/llvm/lib/Analysis/LoopPass.cpp
> b/llvm/lib/Analysis/LoopPass.cpp
> index 9e470e998e672..b720bab454e9b 100644
> --- a/llvm/lib/Analysis/LoopPass.cpp
> +++ b/llvm/lib/Analysis/LoopPass.cpp
> @@ -69,8 +69,7 @@ char PrintLoopPassWrapper::ID = 0;
>
> char LPPassManager::ID = 0;
>
> -LPPassManager::LPPassManager()
> - : FunctionPass(ID), PMDataManager() {
> +LPPassManager::LPPassManager() : FunctionPass(ID) {
> LI = nullptr;
> CurrentLoop = nullptr;
> }
>
> diff --git a/llvm/lib/Analysis/RegionPass.cpp
> b/llvm/lib/Analysis/RegionPass.cpp
> index c20ecff5f9126..10c8569096c6b 100644
> --- a/llvm/lib/Analysis/RegionPass.cpp
> +++ b/llvm/lib/Analysis/RegionPass.cpp
> @@ -30,8 +30,7 @@ using namespace llvm;
>
> char RGPassManager::ID = 0;
>
> -RGPassManager::RGPassManager()
> - : FunctionPass(ID), PMDataManager() {
> +RGPassManager::RGPassManager() : FunctionPass(ID) {
> RI = nullptr;
> CurrentRegion = nullptr;
> }
>
> diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
> b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
> index dc5a4d8f85aaa..1d0c106fd5dbd 100644
> --- a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
> +++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp
> @@ -29,7 +29,7 @@
> using namespace llvm;
>
> InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
> - : Renderers(MaxRenderers), MIs() {}
> + : Renderers(MaxRenderers) {}
>
> InstructionSelector::InstructionSelector() = default;
>
>
> diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
> b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
> index 7e43a0cbbe731..2ee9379cb286b 100644
> --- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
> +++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp
> @@ -185,7 +185,7 @@ class Polynomial {
> APInt A;
>
> public:
> - Polynomial(Value *V) : ErrorMSBs((unsigned)-1), V(V), B(), A() {
> + Polynomial(Value *V) : ErrorMSBs((unsigned)-1), V(V) {
> IntegerType *Ty = dyn_cast<IntegerType>(V->getType());
> if (Ty) {
> ErrorMSBs = 0;
> @@ -195,12 +195,12 @@ class Polynomial {
> }
>
> Polynomial(const APInt &A, unsigned ErrorMSBs = 0)
> - : ErrorMSBs(ErrorMSBs), V(nullptr), B(), A(A) {}
> + : ErrorMSBs(ErrorMSBs), V(nullptr), A(A) {}
>
> Polynomial(unsigned BitWidth, uint64_t A, unsigned ErrorMSBs = 0)
> - : ErrorMSBs(ErrorMSBs), V(nullptr), B(), A(BitWidth, A) {}
> + : ErrorMSBs(ErrorMSBs), V(nullptr), A(BitWidth, A) {}
>
> - Polynomial() : ErrorMSBs((unsigned)-1), V(nullptr), B(), A() {}
> + Polynomial() : ErrorMSBs((unsigned)-1), V(nullptr) {}
>
> /// Increment and clamp the number of undefined bits.
> void incErrorMSBs(unsigned amt) {
> @@ -677,7 +677,7 @@ struct VectorInfo {
> FixedVectorType *const VTy;
>
> VectorInfo(FixedVectorType *VTy)
> - : BB(nullptr), PV(nullptr), LIs(), Is(), SVI(nullptr), VTy(VTy) {
> + : BB(nullptr), PV(nullptr), SVI(nullptr), VTy(VTy) {
> EI = new ElementInfo[VTy->getNumElements()];
> }
>
>
> diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
> b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
> index d0323eaf3d784..f144639770bca 100644
> --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
> +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
> @@ -182,8 +182,7 @@ static void handleYAMLDiag(const SMDiagnostic &Diag,
> void *Context) {
> MIRParserImpl::MIRParserImpl(std::unique_ptr<MemoryBuffer> Contents,
> StringRef Filename, LLVMContext &Context,
> std::function<void(Function &)> Callback)
> - : SM(),
> - Context(Context),
> + : Context(Context),
> In(SM.getMemoryBuffer(SM.AddNewSourceBuffer(std::move(Contents),
> SMLoc()))
> ->getBuffer(),
> nullptr, handleYAMLDiag, this),
>
> diff --git a/llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
> b/llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
> index 59fc23983d3d4..5347a7b0d890a 100644
> --- a/llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
> +++ b/llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
> @@ -22,8 +22,7 @@
> using namespace llvm;
>
> DiagnosticInfoMIROptimization::MachineArgument::MachineArgument(
> - StringRef MKey, const MachineInstr &MI)
> - : Argument() {
> + StringRef MKey, const MachineInstr &MI) {
> Key = std::string(MKey);
>
> raw_string_ostream OS(Val);
>
> diff --git a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
> b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
> index 6e05de888cc01..a61a2b2728fa6 100644
> --- a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
> +++ b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp
> @@ -30,8 +30,7 @@ using namespace llvm;
> ScoreboardHazardRecognizer::ScoreboardHazardRecognizer(
> const InstrItineraryData *II, const ScheduleDAG *SchedDAG,
> const char *ParentDebugType)
> - : ScheduleHazardRecognizer(), DebugType(ParentDebugType),
> ItinData(II),
> - DAG(SchedDAG) {
> + : DebugType(ParentDebugType), ItinData(II), DAG(SchedDAG) {
> (void)DebugType;
> // Determine the maximum depth of any itinerary. This determines the
> depth of
> // the scoreboard. We always make the scoreboard at least 1 cycle deep
> to
>
> diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
> b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
> index d1c2cdeb133b8..697d9df547797 100644
> --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
> +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
> @@ -108,8 +108,7 @@ static void GetObjCImageInfo(Module &M, unsigned
> &Version, unsigned &Flags,
> // ELF
>
> //===----------------------------------------------------------------------===//
>
> -TargetLoweringObjectFileELF::TargetLoweringObjectFileELF()
> - : TargetLoweringObjectFile() {
> +TargetLoweringObjectFileELF::TargetLoweringObjectFileELF() {
> SupportDSOLocalEquivalentLowering = true;
> }
>
> @@ -1139,8 +1138,7 @@ TargetLoweringObjectFileELF::InitializeELF(bool
> UseInitArray_) {
> // MachO
>
> //===----------------------------------------------------------------------===//
>
> -TargetLoweringObjectFileMachO::TargetLoweringObjectFileMachO()
> - : TargetLoweringObjectFile() {
> +TargetLoweringObjectFileMachO::TargetLoweringObjectFileMachO() {
> SupportIndirectSymViaGOTPCRel = true;
> }
>
> @@ -2543,8 +2541,7 @@ MCSection
> *TargetLoweringObjectFileXCOFF::getSectionForTOCEntry(
>
> //===----------------------------------------------------------------------===//
> // GOFF
>
> //===----------------------------------------------------------------------===//
> -TargetLoweringObjectFileGOFF::TargetLoweringObjectFileGOFF()
> - : TargetLoweringObjectFile() {}
> +TargetLoweringObjectFileGOFF::TargetLoweringObjectFileGOFF() {}
>
> MCSection *TargetLoweringObjectFileGOFF::getExplicitSectionGlobal(
> const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM)
> const {
>
> diff --git a/llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp
> b/llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp
> index ac217df1ee48c..2524e10cb6c53 100644
> --- a/llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp
> +++ b/llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp
> @@ -23,7 +23,7 @@ using namespace llvm::pdb;
> NativeEnumTypes::NativeEnumTypes(NativeSession &PDBSession,
> LazyRandomTypeCollection &Types,
> std::vector<codeview::TypeLeafKind>
> Kinds)
> - : Matches(), Index(0), Session(PDBSession) {
> + : Index(0), Session(PDBSession) {
> Optional<TypeIndex> TI = Types.getFirst();
> while (TI) {
> CVType CVT = Types.getType(*TI);
>
> diff --git a/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
> b/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
> index e15bce0d6c4bb..1fb37ce7c57c0 100644
> --- a/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
> +++ b/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
> @@ -96,7 +96,7 @@ class GDBJITRegistrationListener : public
> JITEventListener {
>
> public:
> /// Instantiates the JIT service.
> - GDBJITRegistrationListener() : ObjectBufferMap() {}
> + GDBJITRegistrationListener() {}
>
> /// Unregisters each object that was previously registered and releases
> all
> /// internal resources.
>
> diff --git a/llvm/lib/IR/LegacyPassManager.cpp
> b/llvm/lib/IR/LegacyPassManager.cpp
> index bb72bec93066f..4357c95aa9f6d 100644
> --- a/llvm/lib/IR/LegacyPassManager.cpp
> +++ b/llvm/lib/IR/LegacyPassManager.cpp
> @@ -256,9 +256,9 @@ class FunctionPassManagerImpl : public Pass,
> bool wasRun;
> public:
> static char ID;
> - explicit FunctionPassManagerImpl() :
> - Pass(PT_PassManager, ID), PMDataManager(),
> - PMTopLevelManager(new FPPassManager()), wasRun(false) {}
> + explicit FunctionPassManagerImpl()
> + : Pass(PT_PassManager, ID), PMTopLevelManager(new FPPassManager()),
> + wasRun(false) {}
>
> /// \copydoc FunctionPassManager::add()
> void add(Pass *P) {
> @@ -387,8 +387,7 @@ namespace {
> class MPPassManager : public Pass, public PMDataManager {
> public:
> static char ID;
> - explicit MPPassManager() :
> - Pass(PT_PassManager, ID), PMDataManager() { }
> + explicit MPPassManager() : Pass(PT_PassManager, ID) {}
>
> // Delete on the fly managers.
> ~MPPassManager() override {
> @@ -478,9 +477,8 @@ class PassManagerImpl : public Pass,
>
> public:
> static char ID;
> - explicit PassManagerImpl() :
> - Pass(PT_PassManager, ID), PMDataManager(),
> - PMTopLevelManager(new MPPassManager()) {}
> + explicit PassManagerImpl()
> + : Pass(PT_PassManager, ID), PMTopLevelManager(new MPPassManager())
> {}
>
> /// \copydoc PassManager::add()
> void add(Pass *P) {
>
> diff --git a/llvm/lib/IR/Module.cpp b/llvm/lib/IR/Module.cpp
> index a0485a59d0e08..b3b4b8a80a1c5 100644
> --- a/llvm/lib/IR/Module.cpp
> +++ b/llvm/lib/IR/Module.cpp
> @@ -73,8 +73,7 @@ template class llvm::SymbolTableListTraits<GlobalIFunc>;
>
> Module::Module(StringRef MID, LLVMContext &C)
> : Context(C), ValSymTab(std::make_unique<ValueSymbolTable>(-1)),
> - Materializer(), ModuleID(std::string(MID)),
> - SourceFileName(std::string(MID)), DL("") {
> + ModuleID(std::string(MID)), SourceFileName(std::string(MID)),
> DL("") {
> Context.addModule(this);
> }
>
>
> diff --git a/llvm/lib/InterfaceStub/IFSStub.cpp
> b/llvm/lib/InterfaceStub/IFSStub.cpp
> index 008263f8db9fb..bbc91ada1ded6 100644
> --- a/llvm/lib/InterfaceStub/IFSStub.cpp
> +++ b/llvm/lib/InterfaceStub/IFSStub.cpp
> @@ -29,7 +29,7 @@ IFSStub::IFSStub(IFSStub &&Stub) {
> Symbols = std::move(Stub.Symbols);
> }
>
> -IFSStubTriple::IFSStubTriple(IFSStubTriple const &Stub) : IFSStub() {
> +IFSStubTriple::IFSStubTriple(IFSStubTriple const &Stub) {
> IfsVersion = Stub.IfsVersion;
> Target = Stub.Target;
> SoName = Stub.SoName;
> @@ -37,7 +37,7 @@ IFSStubTriple::IFSStubTriple(IFSStubTriple const &Stub)
> : IFSStub() {
> Symbols = Stub.Symbols;
> }
>
> -IFSStubTriple::IFSStubTriple(IFSStub const &Stub) : IFSStub() {
> +IFSStubTriple::IFSStubTriple(IFSStub const &Stub) {
> IfsVersion = Stub.IfsVersion;
> Target = Stub.Target;
> SoName = Stub.SoName;
>
> diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp
> b/llvm/lib/MC/MCParser/AsmParser.cpp
> index 705f7159d55b5..5c94174aa161f 100644
> --- a/llvm/lib/MC/MCParser/AsmParser.cpp
> +++ b/llvm/lib/MC/MCParser/AsmParser.cpp
> @@ -159,7 +159,7 @@ class AsmParser : public MCAsmParser {
> int64_t LineNumber;
> SMLoc Loc;
> unsigned Buf;
> - CppHashInfoTy() : Filename(), LineNumber(0), Loc(), Buf(0) {}
> + CppHashInfoTy() : LineNumber(0), Buf(0) {}
> };
> CppHashInfoTy CppHashInfo;
>
>
> diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp
> b/llvm/lib/MC/MCParser/MasmParser.cpp
> index f1704cef46ace..e2dfd339e93e2 100644
> --- a/llvm/lib/MC/MCParser/MasmParser.cpp
> +++ b/llvm/lib/MC/MCParser/MasmParser.cpp
> @@ -424,7 +424,7 @@ class MasmParser : public MCAsmParser {
> int64_t LineNumber;
> SMLoc Loc;
> unsigned Buf;
> - CppHashInfoTy() : Filename(), LineNumber(0), Loc(), Buf(0) {}
> + CppHashInfoTy() : LineNumber(0), Buf(0) {}
> };
> CppHashInfoTy CppHashInfo;
>
>
> diff --git a/llvm/lib/MCA/Stages/DispatchStage.cpp
> b/llvm/lib/MCA/Stages/DispatchStage.cpp
> index 5385142698e67..66228bd5a8629 100644
> --- a/llvm/lib/MCA/Stages/DispatchStage.cpp
> +++ b/llvm/lib/MCA/Stages/DispatchStage.cpp
> @@ -30,7 +30,7 @@ DispatchStage::DispatchStage(const MCSubtargetInfo
> &Subtarget,
> unsigned MaxDispatchWidth, RetireControlUnit
> &R,
> RegisterFile &F)
> : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
> - CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) {
> + CarryOver(0U), STI(Subtarget), RCU(R), PRF(F) {
> if (!DispatchWidth)
> DispatchWidth = Subtarget.getSchedModel().IssueWidth;
> }
>
> diff --git a/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
> b/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
> index fa5c0fc66b9ed..abfbc80f17c91 100644
> --- a/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
> +++ b/llvm/lib/MCA/Stages/InOrderIssueStage.cpp
> @@ -47,7 +47,7 @@ InOrderIssueStage::InOrderIssueStage(const
> MCSubtargetInfo &STI,
> RegisterFile &PRF, CustomBehaviour
> &CB,
> LSUnit &LSU)
> : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU),
> - NumIssued(), SI(), CarryOver(), Bandwidth(), LastWriteBackCycle() {}
> + NumIssued(), CarryOver(), Bandwidth(), LastWriteBackCycle() {}
>
> unsigned InOrderIssueStage::getIssueWidth() const {
> return STI.getSchedModel().IssueWidth;
>
> diff --git a/llvm/lib/Remarks/BitstreamRemarkSerializer.cpp
> b/llvm/lib/Remarks/BitstreamRemarkSerializer.cpp
> index 36ba935647715..0810bf531db8b 100644
> --- a/llvm/lib/Remarks/BitstreamRemarkSerializer.cpp
> +++ b/llvm/lib/Remarks/BitstreamRemarkSerializer.cpp
> @@ -18,7 +18,7 @@ using namespace llvm::remarks;
>
> BitstreamRemarkSerializerHelper::BitstreamRemarkSerializerHelper(
> BitstreamRemarkContainerType ContainerType)
> - : Encoded(), R(), Bitstream(Encoded), ContainerType(ContainerType) {}
> + : Bitstream(Encoded), ContainerType(ContainerType) {}
>
> static void push(SmallVectorImpl<uint64_t> &R, StringRef Str) {
> append_range(R, Str);
>
> diff --git a/llvm/lib/Remarks/RemarkStreamer.cpp
> b/llvm/lib/Remarks/RemarkStreamer.cpp
> index 2f00b8e736700..543b00723659e 100644
> --- a/llvm/lib/Remarks/RemarkStreamer.cpp
> +++ b/llvm/lib/Remarks/RemarkStreamer.cpp
> @@ -26,7 +26,7 @@ static cl::opt<cl::boolOrDefault> EnableRemarksSection(
> RemarkStreamer::RemarkStreamer(
> std::unique_ptr<remarks::RemarkSerializer> RemarkSerializer,
> Optional<StringRef> FilenameIn)
> - : PassFilter(), RemarkSerializer(std::move(RemarkSerializer)),
> + : RemarkSerializer(std::move(RemarkSerializer)),
> Filename(FilenameIn ? Optional<std::string>(FilenameIn->str()) :
> None) {}
>
> Error RemarkStreamer::setFilter(StringRef Filter) {
>
> diff --git a/llvm/lib/Remarks/RemarkStringTable.cpp
> b/llvm/lib/Remarks/RemarkStringTable.cpp
> index 5f462f01bb9a6..03d93baba0380 100644
> --- a/llvm/lib/Remarks/RemarkStringTable.cpp
> +++ b/llvm/lib/Remarks/RemarkStringTable.cpp
> @@ -20,7 +20,7 @@
> using namespace llvm;
> using namespace llvm::remarks;
>
> -StringTable::StringTable(const ParsedStringTable &Other) : StrTab() {
> +StringTable::StringTable(const ParsedStringTable &Other) {
> for (unsigned i = 0, e = Other.size(); i < e; ++i)
> if (Expected<StringRef> MaybeStr = Other[i])
> add(*MaybeStr);
>
> diff --git a/llvm/lib/Remarks/YAMLRemarkParser.cpp
> b/llvm/lib/Remarks/YAMLRemarkParser.cpp
> index 3d9996c931aeb..a32629c9f557c 100644
> --- a/llvm/lib/Remarks/YAMLRemarkParser.cpp
> +++ b/llvm/lib/Remarks/YAMLRemarkParser.cpp
> @@ -171,7 +171,7 @@ YAMLRemarkParser::YAMLRemarkParser(StringRef Buf)
>
> YAMLRemarkParser::YAMLRemarkParser(StringRef Buf,
> Optional<ParsedStringTable> StrTab)
> - : RemarkParser{Format::YAML}, StrTab(std::move(StrTab)),
> LastErrorMessage(),
> + : RemarkParser{Format::YAML}, StrTab(std::move(StrTab)),
> SM(setupSM(LastErrorMessage)), Stream(Buf, SM),
> YAMLIt(Stream.begin()) {}
>
> Error YAMLRemarkParser::error(StringRef Message, yaml::Node &Node) {
>
> diff --git a/llvm/lib/Support/YAMLParser.cpp
> b/llvm/lib/Support/YAMLParser.cpp
> index 2adf37a511d15..0ba019b3c46a5 100644
> --- a/llvm/lib/Support/YAMLParser.cpp
> +++ b/llvm/lib/Support/YAMLParser.cpp
> @@ -1841,11 +1841,11 @@ bool Scanner::fetchMoreTokens() {
>
> Stream::Stream(StringRef Input, SourceMgr &SM, bool ShowColors,
> std::error_code *EC)
> - : scanner(new Scanner(Input, SM, ShowColors, EC)), CurrentDoc() {}
> + : scanner(new Scanner(Input, SM, ShowColors, EC)) {}
>
> Stream::Stream(MemoryBufferRef InputBuffer, SourceMgr &SM, bool
> ShowColors,
> std::error_code *EC)
> - : scanner(new Scanner(InputBuffer, SM, ShowColors, EC)), CurrentDoc()
> {}
> + : scanner(new Scanner(InputBuffer, SM, ShowColors, EC)) {}
>
> Stream::~Stream() = default;
>
>
> diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
> b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
> index f7d3dd0bc2225..672739f255991 100644
> --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
> +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp
> @@ -228,7 +228,6 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT,
> const std::string &CPU,
> IsLittle(LittleEndian),
> MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),
> MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride),
> TargetTriple(TT),
> - FrameLowering(),
> InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)),
> TSInfo(),
> TLInfo(TM, *this) {
> if (AArch64::isX18ReservedByDefault(TT))
>
> diff --git a/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
> b/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
> index dfc66f0cb4c16..7ed934cfabc0d 100644
> --- a/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
> +++ b/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
> @@ -25,8 +25,7 @@ void AArch64_ELFTargetObjectFile::Initialize(MCContext
> &Ctx,
> SupportDebugThreadLocalLocation = false;
> }
>
> -AArch64_MachoTargetObjectFile::AArch64_MachoTargetObjectFile()
> - : TargetLoweringObjectFileMachO() {
> +AArch64_MachoTargetObjectFile::AArch64_MachoTargetObjectFile() {
> SupportGOTPCRelWithOffset = false;
> }
>
>
> diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> index 03ef327e93c83..4f8f8078b69d6 100644
> --- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> +++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
> @@ -491,7 +491,7 @@ class AArch64Operand : public MCParsedAsmOperand {
> public:
> AArch64Operand(KindTy K, MCContext &Ctx) : Kind(K), Ctx(Ctx) {}
>
> - AArch64Operand(const AArch64Operand &o) : MCParsedAsmOperand(),
> Ctx(o.Ctx) {
> + AArch64Operand(const AArch64Operand &o) : Ctx(o.Ctx) {
> Kind = o.Kind;
> StartLoc = o.StartLoc;
> EndLoc = o.EndLoc;
>
> diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> index 3d9a626d3ac38..ea8a7c7b83dac 100644
> --- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> +++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
> @@ -472,8 +472,8 @@ class AArch64InstructionSelector : public
> InstructionSelector {
> AArch64InstructionSelector::AArch64InstructionSelector(
> const AArch64TargetMachine &TM, const AArch64Subtarget &STI,
> const AArch64RegisterBankInfo &RBI)
> - : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
> - TRI(*STI.getRegisterInfo()), RBI(RBI),
> + : TM(TM), STI(STI), TII(*STI.getInstrInfo()),
> TRI(*STI.getRegisterInfo()),
> + RBI(RBI),
> #define GET_GLOBALISEL_PREDICATES_INIT
> #include "AArch64GenGlobalISel.inc"
> #undef GET_GLOBALISEL_PREDICATES_INIT
>
> diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
> b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
> index 515a5c63a5596..92d22881f328c 100644
> --- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
> +++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
> @@ -42,8 +42,8 @@
>
> using namespace llvm;
>
> -AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo
> &TRI)
> - : AArch64GenRegisterBankInfo() {
> +AArch64RegisterBankInfo::AArch64RegisterBankInfo(
> + const TargetRegisterInfo &TRI) {
> static llvm::once_flag InitializeRegisterBankFlag;
>
> static auto InitializeRegisterBankOnce = [&]() {
>
> diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h
> b/llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h
> index 22be014813b03..5ba9b2cd187e7 100644
> --- a/llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h
> +++ b/llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h
> @@ -26,7 +26,7 @@ class AMDGPUAAResult : public
> AAResultBase<AMDGPUAAResult> {
> const DataLayout &DL;
>
> public:
> - explicit AMDGPUAAResult(const DataLayout &DL) : AAResultBase(), DL(DL)
> {}
> + explicit AMDGPUAAResult(const DataLayout &DL) : DL(DL) {}
> AMDGPUAAResult(AMDGPUAAResult &&Arg)
> : AAResultBase(std::move(Arg)), DL(Arg.DL) {}
>
>
> diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
> b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
> index e16bead81b65e..e5c5d36d1d4fa 100644
> --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
> +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
> @@ -46,8 +46,7 @@ static cl::opt<bool> AllowRiskySelect(
> AMDGPUInstructionSelector::AMDGPUInstructionSelector(
> const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI,
> const AMDGPUTargetMachine &TM)
> - : InstructionSelector(), TII(*STI.getInstrInfo()),
> - TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),
> + : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
> TM(TM),
> STI(STI),
>
> EnableLateStructurizeCFG(AMDGPUTargetMachine::EnableLateStructurizeCFG),
> #define GET_GLOBALISEL_PREDICATES_INIT
>
> diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
> b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
> index c97223b047e88..fb6a64b75c20f 100644
> --- a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
> +++ b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
> @@ -356,7 +356,7 @@ class AMDGPULibFuncImpl : public AMDGPULibFuncBase {
> /// Wrapper class for AMDGPULIbFuncImpl
> class AMDGPULibFunc : public AMDGPULibFuncBase {
> public:
> - explicit AMDGPULibFunc() : Impl(std::unique_ptr<AMDGPULibFuncImpl>()) {}
> + explicit AMDGPULibFunc() {}
> AMDGPULibFunc(const AMDGPULibFunc &F);
> /// Clone a mangled library func with the Id \p Id and argument info
> from \p
> /// CopyFrom.
>
> diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
> b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
> index c60012bcfe2e8..ab463ce8940dc 100644
> --- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
> +++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
> @@ -193,9 +193,7 @@ class ApplyRegBankMapping final : public
> GISelChangeObserver {
>
> }
> AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const GCNSubtarget &ST)
> - : AMDGPUGenRegisterBankInfo(),
> - Subtarget(ST),
> - TRI(Subtarget.getRegisterInfo()),
> + : Subtarget(ST), TRI(Subtarget.getRegisterInfo()),
> TII(Subtarget.getInstrInfo()) {
>
> // HACK: Until this is fully tablegen'd.
>
> diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
> b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
> index 2bb59086f391b..c71205b17a1a5 100644
> --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
> +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
> @@ -62,7 +62,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {
>
> public:
> AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)
> - : MCParsedAsmOperand(), Kind(Kind_), AsmParser(AsmParser_) {}
> + : Kind(Kind_), AsmParser(AsmParser_) {}
>
> using Ptr = std::unique_ptr<AMDGPUOperand>;
>
>
> diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
> b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
> index 7708579a4491d..ded3fb7ab8d9f 100644
> --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
> +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp
> @@ -15,8 +15,7 @@
> using namespace llvm;
>
> AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
> - const MCTargetOptions &Options)
> - : MCAsmInfoELF() {
> + const MCTargetOptions &Options) {
> CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4;
> StackGrowsUp = true;
> HasSingleParameterDotFile = false;
>
> diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
> b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
> index f083fa6662e93..0d201a67af461 100644
> --- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
> +++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp
> @@ -164,7 +164,7 @@ static bool getBaseOffset(const MachineInstr &MI,
> const MachineOperand *&BaseOp,
>
> ARMBankConflictHazardRecognizer::ARMBankConflictHazardRecognizer(
> const ScheduleDAG *DAG, int64_t CPUBankMask, bool
> CPUAssumeITCMConflict)
> - : ScheduleHazardRecognizer(), MF(DAG->MF),
> DL(DAG->MF.getDataLayout()),
> + : MF(DAG->MF), DL(DAG->MF.getDataLayout()),
> DataMask(DataBankMask.getNumOccurrences() ? int64_t(DataBankMask)
> : CPUBankMask),
> AssumeITCMBankConflict(AssumeITCMConflict.getNumOccurrences()
>
> diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.h
> b/llvm/lib/Target/ARM/ARMHazardRecognizer.h
> index c1f1bcd0a629b..66a1477e5e082 100644
> --- a/llvm/lib/Target/ARM/ARMHazardRecognizer.h
> +++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.h
> @@ -34,7 +34,7 @@ class ARMHazardRecognizerFPMLx : public
> ScheduleHazardRecognizer {
> unsigned FpMLxStalls = 0;
>
> public:
> - ARMHazardRecognizerFPMLx() : ScheduleHazardRecognizer() { MaxLookAhead
> = 1; }
> + ARMHazardRecognizerFPMLx() { MaxLookAhead = 1; }
>
> HazardType getHazardType(SUnit *SU, int Stalls) override;
> void Reset() override;
>
> diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
> b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
> index 5dee5e04af815..00db13f2eb520 100644
> --- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
> +++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
> @@ -28,8 +28,7 @@
> #include "llvm/MC/MCInst.h"
> using namespace llvm;
>
> -ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
> - : ARMBaseInstrInfo(STI), RI() {}
> +ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) :
> ARMBaseInstrInfo(STI) {}
>
> /// Return the noop instruction to use for a noop.
> MCInst ARMInstrInfo::getNop() const {
>
> diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
> b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
> index 8be4e3f160e30..188b5562cac93 100644
> --- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
> +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
> @@ -171,8 +171,8 @@ createARMInstructionSelector(const
> ARMBaseTargetMachine &TM,
> ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine
> &TM,
> const ARMSubtarget &STI,
> const ARMRegisterBankInfo
> &RBI)
> - : InstructionSelector(), TII(*STI.getInstrInfo()),
> - TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI),
> Opcodes(STI),
> + : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM),
> RBI(RBI),
> + STI(STI), Opcodes(STI),
> #define GET_GLOBALISEL_PREDICATES_INIT
> #include "ARMGenGlobalISel.inc"
> #undef GET_GLOBALISEL_PREDICATES_INIT
>
> diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
> b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
> index 1a7f10a13ed30..2523752a717e4 100644
> --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
> +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
> @@ -129,8 +129,7 @@ static void checkValueMappings() {
> } // end namespace arm
> } // end namespace llvm
>
> -ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
> - : ARMGenRegisterBankInfo() {
> +ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) {
> // We have only one set of register banks, whatever the subtarget
> // is. Therefore, the initialization of the RegBanks table should be
> // done only once. Indeed the table of all register banks
>
> diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
> b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
> index 6649750bb3883..ff4647dd46fd9 100644
> --- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
> +++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
> @@ -15,4 +15,4 @@ using namespace llvm;
>
> void ARMRegisterInfo::anchor() { }
>
> -ARMRegisterInfo::ARMRegisterInfo() : ARMBaseRegisterInfo() {}
> +ARMRegisterInfo::ARMRegisterInfo() {}
>
> diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.h
> b/llvm/lib/Target/ARM/ARMTargetObjectFile.h
> index f86774beb397f..47334b9a8a453 100644
> --- a/llvm/lib/Target/ARM/ARMTargetObjectFile.h
> +++ b/llvm/lib/Target/ARM/ARMTargetObjectFile.h
> @@ -17,8 +17,7 @@ namespace llvm {
>
> class ARMElfTargetObjectFile : public TargetLoweringObjectFileELF {
> public:
> - ARMElfTargetObjectFile()
> - : TargetLoweringObjectFileELF() {
> + ARMElfTargetObjectFile() {
> PLTRelativeVariantKind = MCSymbolRefExpr::VK_ARM_PREL31;
> }
>
>
> diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> index c8cec88d6e11d..c7734cc2cf11d 100644
> --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
> @@ -921,7 +921,7 @@ class ARMOperand : public MCParsedAsmOperand {
> };
>
> public:
> - ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
> + ARMOperand(KindTy K) : Kind(K) {}
>
> /// getStartLoc - Get the location of the first token of this operand.
> SMLoc getStartLoc() const override { return StartLoc; }
>
> diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
> b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
> index 4b18f5e20d406..1a36c2ca9152e 100644
> --- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
> +++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
> @@ -21,7 +21,7 @@
> using namespace llvm;
>
> Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
> - : ARMBaseInstrInfo(STI), RI() {}
> + : ARMBaseInstrInfo(STI) {}
>
> /// Return the noop instruction to use for a noop.
> MCInst Thumb1InstrInfo::getNop() const {
>
> diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
> b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
> index 4da6f6ab6994f..5d2bc4ebe1917 100644
> --- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
> +++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
> @@ -37,7 +37,7 @@ extern cl::opt<bool> ReuseFrameIndexVals;
>
> using namespace llvm;
>
> -ThumbRegisterInfo::ThumbRegisterInfo() : ARMBaseRegisterInfo() {}
> +ThumbRegisterInfo::ThumbRegisterInfo() {}
>
> const TargetRegisterClass *
> ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass
> *RC,
>
> diff --git a/llvm/lib/Target/AVR/AVRSubtarget.cpp
> b/llvm/lib/Target/AVR/AVRSubtarget.cpp
> index 990e1c57e63f3..820efe79bf8af 100644
> --- a/llvm/lib/Target/AVR/AVRSubtarget.cpp
> +++ b/llvm/lib/Target/AVR/AVRSubtarget.cpp
> @@ -39,8 +39,6 @@ AVRSubtarget::AVRSubtarget(const Triple &TT, const
> std::string &CPU,
> m_supportsRMW(false), m_supportsMultiplication(false),
> m_hasBREAK(false),
> m_hasTinyEncoding(false), m_hasMemMappedGPR(false),
> m_FeatureSetDummy(false),
> -
> - InstrInfo(), FrameLowering(),
> TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)), TSInfo() {
> // Parse features string.
> ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
>
> diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
> b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
> index 95c737aa272ef..f19e7840eb310 100644
> --- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
> +++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp
> @@ -107,13 +107,13 @@ class AVROperand : public MCParsedAsmOperand {
>
> public:
> AVROperand(StringRef Tok, SMLoc const &S)
> - : Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
> + : Kind(k_Token), Tok(Tok), Start(S), End(S) {}
> AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
> - : Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S),
> End(E) {}
> + : Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
> AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
> - : Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
> + : Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
> AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const
> &E)
> - : Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
> + : Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
>
> struct RegisterImmediate {
> unsigned Reg;
>
> diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
> b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
> index 50298bf5e943e..d55510a2455c6 100644
> --- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
> +++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp
> @@ -101,10 +101,10 @@ struct BPFOperand : public MCParsedAsmOperand {
> ImmOp Imm;
> };
>
> - BPFOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
> + BPFOperand(KindTy K) : Kind(K) {}
>
> public:
> - BPFOperand(const BPFOperand &o) : MCParsedAsmOperand() {
> + BPFOperand(const BPFOperand &o) {
> Kind = o.Kind;
> StartLoc = o.StartLoc;
> EndLoc = o.EndLoc;
>
> diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp
> b/llvm/lib/Target/BPF/BPFSubtarget.cpp
> index 77e3cd393f875..e4d98b85e58b8 100644
> --- a/llvm/lib/Target/BPF/BPFSubtarget.cpp
> +++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp
> @@ -59,6 +59,6 @@ void BPFSubtarget::initSubtargetFeatures(StringRef CPU,
> StringRef FS) {
>
> BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
> const std::string &FS, const TargetMachine &TM)
> - : BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),
> + : BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
> FrameLowering(initializeSubtargetDependencies(CPU, FS)),
> TLInfo(TM, *this) {}
>
> diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
> b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
> index d131cf896834d..58f5ea78c5416 100644
> --- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
> +++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
> @@ -211,12 +211,10 @@ struct HexagonOperand : public MCParsedAsmOperand {
> struct ImmTy Imm;
> };
>
> - HexagonOperand(KindTy K, MCContext &Context)
> - : MCParsedAsmOperand(), Kind(K), Context(Context) {}
> + HexagonOperand(KindTy K, MCContext &Context) : Kind(K),
> Context(Context) {}
>
> public:
> - HexagonOperand(const HexagonOperand &o)
> - : MCParsedAsmOperand(), Context(o.Context) {
> + HexagonOperand(const HexagonOperand &o) : Context(o.Context) {
> Kind = o.Kind;
> StartLoc = o.StartLoc;
> EndLoc = o.EndLoc;
>
> diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> index 2679e399852f2..091542f2e76a3 100644
> --- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> +++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
> @@ -1652,7 +1652,7 @@ struct WeightedLeaf {
> int Weight;
> int InsertionOrder;
>
> - WeightedLeaf() : Value(SDValue()) { }
> + WeightedLeaf() {}
>
> WeightedLeaf(SDValue Value, int Weight, int InsertionOrder) :
> Value(Value), Weight(Weight), InsertionOrder(InsertionOrder) {
>
> diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> index 5f094dfeb95c9..a47d414af831f 100644
> --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp
> @@ -204,7 +204,7 @@ HexagonMCChecker::HexagonMCChecker(MCContext &Context,
> MCInstrInfo const &MCII,
> MCSubtargetInfo const &STI, MCInst
> &mcb,
> MCRegisterInfo const &ri, bool
> ReportErrors)
> : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),
> - ReportErrors(ReportErrors), ReversePairs() {
> + ReportErrors(ReportErrors) {
> init();
> }
>
> @@ -212,8 +212,7 @@ HexagonMCChecker::HexagonMCChecker(HexagonMCChecker
> const &Other,
> MCSubtargetInfo const &STI,
> bool CopyReportErrors)
> : Context(Other.Context), MCB(Other.MCB), RI(Other.RI),
> MCII(Other.MCII),
> - STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors :
> false),
> - ReversePairs() {
> + STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors :
> false) {
> init();
> }
>
>
> diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
> b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
> index a994bd7e57a40..660215ca74353 100644
> --- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
> +++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
> @@ -141,7 +141,7 @@ struct LanaiOperand : public MCParsedAsmOperand {
> struct MemOp Mem;
> };
>
> - explicit LanaiOperand(KindTy Kind) : MCParsedAsmOperand(), Kind(Kind) {}
> + explicit LanaiOperand(KindTy Kind) : Kind(Kind) {}
>
> public:
> // The functions below are used by the autogenerated ASM matcher and
> hence to
>
> diff --git a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
> b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
> index d9d7847a0c5ab..37a4843e1bc40 100644
> --- a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
> +++ b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp
> @@ -43,4 +43,4 @@ LanaiSubtarget::LanaiSubtarget(const Triple
> &TargetTriple, StringRef Cpu,
> CodeGenOpt::Level /*OptLevel*/)
> : LanaiGenSubtargetInfo(TargetTriple, Cpu, /*TuneCPU*/ Cpu,
> FeatureString),
> FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)),
> - InstrInfo(), TLInfo(TM, *this), TSInfo() {}
> + TLInfo(TM, *this) {}
>
> diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
> b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
> index c1677baf52a7a..13cba8b079a9b 100644
> --- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
> +++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp
> @@ -114,13 +114,14 @@ class MSP430Operand : public MCParsedAsmOperand {
>
> public:
> MSP430Operand(StringRef Tok, SMLoc const &S)
> - : Base(), Kind(k_Tok), Tok(Tok), Start(S), End(S) {}
> + : Kind(k_Tok), Tok(Tok), Start(S), End(S) {}
> MSP430Operand(KindTy Kind, unsigned Reg, SMLoc const &S, SMLoc const &E)
> - : Base(), Kind(Kind), Reg(Reg), Start(S), End(E) {}
> + : Kind(Kind), Reg(Reg), Start(S), End(E) {}
> MSP430Operand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
> - : Base(), Kind(k_Imm), Imm(Imm), Start(S), End(E) {}
> - MSP430Operand(unsigned Reg, MCExpr const *Expr, SMLoc const &S, SMLoc
> const &E)
> - : Base(), Kind(k_Mem), Mem({Reg, Expr}), Start(S), End(E) {}
> + : Kind(k_Imm), Imm(Imm), Start(S), End(E) {}
> + MSP430Operand(unsigned Reg, MCExpr const *Expr, SMLoc const &S,
> + SMLoc const &E)
> + : Kind(k_Mem), Mem({Reg, Expr}), Start(S), End(E) {}
>
> void addRegOperands(MCInst &Inst, unsigned N) const {
> assert((Kind == k_Reg || Kind == k_IndReg || Kind == k_PostIndReg) &&
>
> diff --git a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp
> b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp
> index 2fd58717c4dbe..0604d47597e25 100644
> --- a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp
> +++ b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp
> @@ -57,5 +57,5 @@
> MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef
> FS) {
>
> MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,
> const std::string &FS, const
> TargetMachine &TM)
> - : MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
> FrameLowering(),
> + : MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
> InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM,
> *this) {}
>
> diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> index 01b5dff2e4486..736c41f8ac035 100644
> --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
> @@ -827,8 +827,7 @@ class MipsOperand : public MCParsedAsmOperand {
> } Kind;
>
> public:
> - MipsOperand(KindTy K, MipsAsmParser &Parser)
> - : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}
> + MipsOperand(KindTy K, MipsAsmParser &Parser) : Kind(K),
> AsmParser(Parser) {}
>
> ~MipsOperand() override {
> switch (Kind) {
>
> diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
> b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
> index f6f43da9abf84..563118dfe627d 100644
> --- a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
> +++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp
> @@ -37,7 +37,7 @@ using namespace llvm;
>
> #define DEBUG_TYPE "mips16-registerinfo"
>
> -Mips16RegisterInfo::Mips16RegisterInfo() : MipsRegisterInfo() {}
> +Mips16RegisterInfo::Mips16RegisterInfo() {}
>
> bool Mips16RegisterInfo::requiresRegisterScavenging
> (const MachineFunction &MF) const {
>
> diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
> b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
> index 6d44ce2ab5635..59f158688b163 100644
> --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
> +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
> @@ -80,8 +80,8 @@ class MipsInstructionSelector : public
> InstructionSelector {
> MipsInstructionSelector::MipsInstructionSelector(
> const MipsTargetMachine &TM, const MipsSubtarget &STI,
> const MipsRegisterBankInfo &RBI)
> - : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
> - TRI(*STI.getRegisterInfo()), RBI(RBI),
> + : TM(TM), STI(STI), TII(*STI.getInstrInfo()),
> TRI(*STI.getRegisterInfo()),
> + RBI(RBI),
>
> #define GET_GLOBALISEL_PREDICATES_INIT
> #include "MipsGenGlobalISel.inc"
>
> diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
> b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
> index 04b69c66bc0d1..2cb59e6960313 100644
> --- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
> +++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
> @@ -73,8 +73,7 @@ RegisterBankInfo::ValueMapping ValueMappings[] = {
>
> using namespace llvm;
>
> -MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
> - : MipsGenRegisterBankInfo() {}
> +MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
> {}
>
> const RegisterBank &
> MipsRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass
> &RC,
>
> diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
> b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
> index b05e9ad827c40..d6481793ef495 100644
> --- a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
> +++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp
> @@ -38,7 +38,7 @@ using namespace llvm;
>
> #define DEBUG_TYPE "mips-reg-info"
>
> -MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
> +MipsSERegisterInfo::MipsSERegisterInfo() {}
>
> bool MipsSERegisterInfo::
> requiresRegisterScavenging(const MachineFunction &MF) const {
>
> diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
> b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
> index 953d95e55f658..8df6f13aa68e1 100644
> --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
> +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
> @@ -27,7 +27,7 @@ using namespace llvm;
> // Pin the vtable to this file.
> void NVPTXInstrInfo::anchor() {}
>
> -NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
> +NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {}
>
> void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
> MachineBasicBlock::iterator I,
>
> diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
> b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
> index 05c20369abf45..5a6440c91fcad 100644
> --- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
> +++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
> @@ -49,8 +49,8 @@ NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const
> std::string &CPU,
> const std::string &FS,
> const NVPTXTargetMachine &TM)
> : NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
> - SmVersion(20), TM(TM), InstrInfo(),
> - TLInfo(TM, initializeSubtargetDependencies(CPU, FS)),
> FrameLowering() {}
> + SmVersion(20), TM(TM),
> + TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {}
>
> bool NVPTXSubtarget::hasImageHandles() const {
> // Enable handles for Kepler+, where CUDA supports indirect surfaces and
>
> diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h
> b/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h
> index 366d92a5a8054..4645671a0cd86 100644
> --- a/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h
> +++ b/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h
> @@ -17,7 +17,7 @@ namespace llvm {
>
> class NVPTXTargetObjectFile : public TargetLoweringObjectFile {
> public:
> - NVPTXTargetObjectFile() : TargetLoweringObjectFile() {}
> + NVPTXTargetObjectFile() {}
>
> ~NVPTXTargetObjectFile() override;
>
>
> diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
> b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
> index ded922329ebf6..1f509afb723b4 100644
> --- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
> +++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
> @@ -201,9 +201,10 @@ struct PPCOperand : public MCParsedAsmOperand {
> struct TLSRegOp TLSReg;
> };
>
> - PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
> + PPCOperand(KindTy K) : Kind(K) {}
> +
> public:
> - PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
> + PPCOperand(const PPCOperand &o) {
> Kind = o.Kind;
> StartLoc = o.StartLoc;
> EndLoc = o.EndLoc;
>
> diff --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
> b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
> index 7d64816ed6c7f..0cd8350e3fdda 100644
> --- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
> +++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp
> @@ -65,8 +65,7 @@ class PPCInstructionSelector : public
> InstructionSelector {
> PPCInstructionSelector::PPCInstructionSelector(const PPCTargetMachine &TM,
> const PPCSubtarget &STI,
> const PPCRegisterBankInfo
> &RBI)
> - : InstructionSelector(), TII(*STI.getInstrInfo()),
> - TRI(*STI.getRegisterInfo()), RBI(RBI),
> + : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),
> #define GET_GLOBALISEL_PREDICATES_INIT
> #include "PPCGenGlobalISel.inc"
> #undef GET_GLOBALISEL_PREDICATES_INIT
>
> diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
> b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
> index 6af79324919cc..58165fcaac03f 100644
> --- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
> +++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
> @@ -23,5 +23,4 @@
>
> using namespace llvm;
>
> -PPCRegisterBankInfo::PPCRegisterBankInfo(const TargetRegisterInfo &TRI)
> - : PPCGenRegisterBankInfo() {}
> +PPCRegisterBankInfo::PPCRegisterBankInfo(const TargetRegisterInfo &TRI) {}
>
> diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
> b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
> index 75592dd4c6f54..858e78076b566 100644
> --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
> +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
> @@ -302,10 +302,10 @@ struct RISCVOperand : public MCParsedAsmOperand {
> struct VTypeOp VType;
> };
>
> - RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
> + RISCVOperand(KindTy K) : Kind(K) {}
>
> public:
> - RISCVOperand(const RISCVOperand &o) : MCParsedAsmOperand() {
> + RISCVOperand(const RISCVOperand &o) {
> Kind = o.Kind;
> IsRV64 = o.IsRV64;
> StartLoc = o.StartLoc;
>
> diff --git a/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
> b/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
> index 4d1f47da209d0..8dfd71ac0b6bd 100644
> --- a/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
> +++ b/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
> @@ -69,8 +69,7 @@ class RISCVInstructionSelector : public
> InstructionSelector {
> RISCVInstructionSelector::RISCVInstructionSelector(
> const RISCVTargetMachine &TM, const RISCVSubtarget &STI,
> const RISCVRegisterBankInfo &RBI)
> - : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),
> - TRI(*STI.getRegisterInfo()), RBI(RBI),
> + : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),
> RBI(RBI),
>
> #define GET_GLOBALISEL_PREDICATES_INIT
> #include "RISCVGenGlobalISel.inc"
>
> diff --git a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
> b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
> index bd3b95a98b9f7..4ff3a44f35118 100644
> --- a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
> +++ b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp
> @@ -22,5 +22,4 @@
>
> using namespace llvm;
>
> -RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo
> &TRI)
> - : RISCVGenRegisterBankInfo() {}
> +RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo
> &TRI) {}
>
> diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
> b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
> index 48e6903bd1b12..af3304f0907d0 100644
> --- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
> +++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
> @@ -257,7 +257,7 @@ class SparcOperand : public MCParsedAsmOperand {
> };
>
> public:
> - SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
> + SparcOperand(KindTy K) : Kind(K) {}
>
> bool isToken() const override { return Kind == k_Token; }
> bool isReg() const override { return Kind == k_Register; }
>
> diff --git a/llvm/lib/Target/Sparc/SparcTargetObjectFile.h
> b/llvm/lib/Target/Sparc/SparcTargetObjectFile.h
> index 9bbe602b32b30..f30ddc7b4955d 100644
> --- a/llvm/lib/Target/Sparc/SparcTargetObjectFile.h
> +++ b/llvm/lib/Target/Sparc/SparcTargetObjectFile.h
> @@ -18,9 +18,7 @@ class TargetMachine;
>
> class SparcELFTargetObjectFile : public TargetLoweringObjectFileELF {
> public:
> - SparcELFTargetObjectFile() :
> - TargetLoweringObjectFileELF()
> - {}
> + SparcELFTargetObjectFile() {}
>
> void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
>
>
> diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> index 39a82e2c07e02..cf55318d328df 100644
> --- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> +++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
> @@ -62,8 +62,7 @@ struct SystemZAddressingMode {
> bool IncludesDynAlloc;
>
> SystemZAddressingMode(AddrForm form, DispRange dr)
> - : Form(form), DR(dr), Base(), Disp(0), Index(),
> - IncludesDynAlloc(false) {}
> + : Form(form), DR(dr), Disp(0), IncludesDynAlloc(false) {}
>
> // True if the address can have an index register.
> bool hasIndexField() { return Form != FormBD; }
>
> diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
> b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
> index 0f03d96655bff..75c0d454d9047 100644
> --- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
> +++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp
> @@ -89,7 +89,7 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT,
> const std::string &CPU,
> HasSoftFloat(false), TargetTriple(TT),
> SpecialRegisters(initializeSpecialRegisters()),
> InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM,
> *this),
> - TSInfo(), FrameLowering(SystemZFrameLowering::create(*this)) {}
> + FrameLowering(SystemZFrameLowering::create(*this)) {}
>
> bool SystemZSubtarget::enableSubRegLiveness() const {
> return UseSubRegLiveness;
>
> diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
> b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
> index fd9dc32b04f54..4a318e493c522 100644
> --- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
> +++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
> @@ -210,7 +210,7 @@ class VEOperand : public MCParsedAsmOperand {
> };
>
> public:
> - VEOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
> + VEOperand(KindTy K) : Kind(K) {}
>
> bool isToken() const override { return Kind == k_Token; }
> bool isReg() const override { return Kind == k_Register; }
>
> diff --git a/llvm/lib/Target/VE/VEMachineFunctionInfo.h
> b/llvm/lib/Target/VE/VEMachineFunctionInfo.h
> index 16b25fed3f11d..3160f6a552d78 100644
> --- a/llvm/lib/Target/VE/VEMachineFunctionInfo.h
> +++ b/llvm/lib/Target/VE/VEMachineFunctionInfo.h
> @@ -29,10 +29,9 @@ class VEMachineFunctionInfo : public
> MachineFunctionInfo {
> bool IsLeafProc;
>
> public:
> - VEMachineFunctionInfo()
> - : GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {}
> + VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {}
> explicit VEMachineFunctionInfo(MachineFunction &MF)
> - : GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {}
> + : VarArgsFrameOffset(0), IsLeafProc(false) {}
>
> Register getGlobalBaseReg() const { return GlobalBaseReg; }
> void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }
>
> diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
> b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
> index add3c799f4aa3..103b634ecf5bc 100644
> --- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
> +++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
> @@ -42,9 +42,8 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple
> &TT,
> const std::string &FS,
> const TargetMachine &TM)
> : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
> - TargetTriple(TT), FrameLowering(),
> - InstrInfo(initializeSubtargetDependencies(CPU, FS)), TSInfo(),
> - TLInfo(TM, *this) {}
> + TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU,
> FS)),
> + TSInfo(), TLInfo(TM, *this) {}
>
> bool WebAssemblySubtarget::enableAtomicExpand() const {
> // If atomics are disabled, atomic ops are lowered instead of expanded
>
> diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
> b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
> index 7ed05fd0331dc..5b90c67deae61 100644
> --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
> +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
> @@ -80,9 +80,9 @@ namespace {
> bool NegateIndex = false;
>
> X86ISelAddressMode()
> - : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(),
> Disp(0),
> - Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr),
> ES(nullptr),
> - MCSym(nullptr), JT(-1), SymbolFlags(X86II::MO_NO_FLAG) {}
> + : BaseType(RegBase), Base_FrameIndex(0), Scale(1), Disp(0),
> GV(nullptr),
> + CP(nullptr), BlockAddr(nullptr), ES(nullptr), MCSym(nullptr),
> JT(-1),
> + SymbolFlags(X86II::MO_NO_FLAG) {}
>
> bool hasSymbolicDisplacement() const {
> return GV != nullptr || CP != nullptr || ES != nullptr ||
>
> diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp
> b/llvm/lib/Target/X86/X86InstructionSelector.cpp
> index 8abbaa92c8cf6..28d57ca9ae3c7 100644
> --- a/llvm/lib/Target/X86/X86InstructionSelector.cpp
> +++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp
> @@ -153,8 +153,8 @@ class X86InstructionSelector : public
> InstructionSelector {
> X86InstructionSelector::X86InstructionSelector(const X86TargetMachine &TM,
> const X86Subtarget &STI,
> const X86RegisterBankInfo
> &RBI)
> - : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),
> - TRI(*STI.getRegisterInfo()), RBI(RBI),
> + : TM(TM), STI(STI), TII(*STI.getInstrInfo()),
> TRI(*STI.getRegisterInfo()),
> + RBI(RBI),
> #define GET_GLOBALISEL_PREDICATES_INIT
> #include "X86GenGlobalISel.inc"
> #undef GET_GLOBALISEL_PREDICATES_INIT
>
> diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp
> b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp
> index 9c076d2d67694..497a8f6e065fd 100644
> --- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp
> +++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp
> @@ -25,8 +25,7 @@ using namespace llvm;
> #define GET_TARGET_REGBANK_INFO_IMPL
> #include "X86GenRegisterBankInfo.def"
>
> -X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI)
> - : X86GenRegisterBankInfo() {
> +X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI) {
>
> // validate RegBank initialization.
> const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID);
>
> diff --git a/llvm/lib/Target/XCore/XCoreSubtarget.cpp
> b/llvm/lib/Target/XCore/XCoreSubtarget.cpp
> index 1be707cb488cb..051d51178baa4 100644
> --- a/llvm/lib/Target/XCore/XCoreSubtarget.cpp
> +++ b/llvm/lib/Target/XCore/XCoreSubtarget.cpp
> @@ -26,5 +26,5 @@ void XCoreSubtarget::anchor() { }
>
> XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,
> const std::string &FS, const TargetMachine
> &TM)
> - : XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),
> - FrameLowering(*this), TLInfo(TM, *this), TSInfo() {}
> + : XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
> FrameLowering(*this),
> + TLInfo(TM, *this), TSInfo() {}
>
> diff --git a/llvm/lib/Transforms/IPO/Inliner.cpp
> b/llvm/lib/Transforms/IPO/Inliner.cpp
> index 4e3689f095363..0fef01a47b04b 100644
> --- a/llvm/lib/Transforms/IPO/Inliner.cpp
> +++ b/llvm/lib/Transforms/IPO/Inliner.cpp
> @@ -1073,8 +1073,7 @@
> ModuleInlinerWrapperPass::ModuleInlinerWrapperPass(InlineParams Params,
> bool MandatoryFirst,
> InliningAdvisorMode
> Mode,
> unsigned
> MaxDevirtIterations)
> - : Params(Params), Mode(Mode),
> MaxDevirtIterations(MaxDevirtIterations),
> - PM(), MPM() {
> + : Params(Params), Mode(Mode),
> MaxDevirtIterations(MaxDevirtIterations) {
> // Run the inliner first. The theory is that we are walking bottom-up
> and so
> // the callees have already been fully optimized, and we want to inline
> them
> // into the callers so that our optimizations can reflect that.
>
> diff --git a/llvm/lib/Transforms/IPO/PartialInlining.cpp
> b/llvm/lib/Transforms/IPO/PartialInlining.cpp
> index 2d717475ce7f1..fe9586ce75a62 100644
> --- a/llvm/lib/Transforms/IPO/PartialInlining.cpp
> +++ b/llvm/lib/Transforms/IPO/PartialInlining.cpp
> @@ -169,8 +169,7 @@ struct FunctionOutliningInfo {
> };
>
> struct FunctionOutliningMultiRegionInfo {
> - FunctionOutliningMultiRegionInfo()
> - : ORI() {}
> + FunctionOutliningMultiRegionInfo() {}
>
> // Container for outline regions
> struct OutlineRegionInfo {
>
> diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
> b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
> index 73f208abcb07a..e9c4a56a90c2e 100644
> --- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
> +++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp
> @@ -248,8 +248,7 @@ class PGOCounterPromoter {
> PGOCounterPromoter(
> DenseMap<Loop *, SmallVector<LoadStorePair, 8>> &LoopToCands,
> Loop &CurLoop, LoopInfo &LI, BlockFrequencyInfo *BFI)
> - : LoopToCandidates(LoopToCands), ExitBlocks(), InsertPts(),
> L(CurLoop),
> - LI(LI), BFI(BFI) {
> + : LoopToCandidates(LoopToCands), L(CurLoop), LI(LI), BFI(BFI) {
>
> // Skip collection of ExitBlocks and InsertPts for loops that will
> not be
> // able to have counters promoted.
>
> diff --git a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
> b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
> index 4e4097e13271b..accaa1088d6fd 100644
> --- a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
> +++ b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
> @@ -220,9 +220,7 @@ class LowerMatrixIntrinsics {
> bool IsColumnMajor = true;
>
> public:
> - MatrixTy()
> - : Vectors(),
> - IsColumnMajor(MatrixLayout == MatrixLayoutTy::ColumnMajor) {}
> + MatrixTy() : IsColumnMajor(MatrixLayout ==
> MatrixLayoutTy::ColumnMajor) {}
> MatrixTy(ArrayRef<Value *> Vectors)
> : Vectors(Vectors.begin(), Vectors.end()),
> IsColumnMajor(MatrixLayout == MatrixLayoutTy::ColumnMajor) {}
> @@ -1832,7 +1830,7 @@ class LowerMatrixIntrinsics {
> const DenseMap<Value *, SmallPtrSet<Value *, 2>>
> &Shared,
> const SmallSetVector<Value *, 32> &ExprsInSubprogram,
> Value *Leaf)
> - : Str(), Stream(Str), DL(DL), Inst2Matrix(Inst2Matrix),
> Shared(Shared),
> + : Stream(Str), DL(DL), Inst2Matrix(Inst2Matrix), Shared(Shared),
> ExprsInSubprogram(ExprsInSubprogram), Leaf(Leaf) {}
>
> void indent(unsigned N) {
>
> diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h
> b/llvm/lib/Transforms/Vectorize/VPlan.h
> index a8102c0b07b88..503cb1123e4e5 100644
> --- a/llvm/lib/Transforms/Vectorize/VPlan.h
> +++ b/llvm/lib/Transforms/Vectorize/VPlan.h
> @@ -198,8 +198,8 @@ struct VPTransformState {
> VPTransformState(ElementCount VF, unsigned UF, LoopInfo *LI,
> DominatorTree *DT, IRBuilder<> &Builder,
> InnerLoopVectorizer *ILV, VPlan *Plan)
> - : VF(VF), UF(UF), Instance(), LI(LI), DT(DT), Builder(Builder),
> ILV(ILV),
> - Plan(Plan) {}
> + : VF(VF), UF(UF), LI(LI), DT(DT), Builder(Builder), ILV(ILV),
> Plan(Plan) {
> + }
>
> /// The chosen Vectorization and Unroll Factors of the loop being
> vectorized.
> ElementCount VF;
>
> diff --git a/llvm/tools/dsymutil/BinaryHolder.h
> b/llvm/tools/dsymutil/BinaryHolder.h
> index 5e81fe4b93b14..6245e49247337 100644
> --- a/llvm/tools/dsymutil/BinaryHolder.h
> +++ b/llvm/tools/dsymutil/BinaryHolder.h
> @@ -103,7 +103,7 @@ class BinaryHolder {
> std::string Filename;
> TimestampTy Timestamp;
>
> - KeyTy() : Filename(), Timestamp() {}
> + KeyTy() {}
> KeyTy(StringRef Filename, TimestampTy Timestamp)
> : Filename(Filename.str()), Timestamp(Timestamp) {}
> };
>
> diff --git a/llvm/tools/dsymutil/Reproducer.cpp
> b/llvm/tools/dsymutil/Reproducer.cpp
> index 5c60758c6f80e..4f2e0db297e5c 100644
> --- a/llvm/tools/dsymutil/Reproducer.cpp
> +++ b/llvm/tools/dsymutil/Reproducer.cpp
> @@ -27,7 +27,7 @@ Reproducer::Reproducer() : VFS(vfs::getRealFileSystem())
> {}
> Reproducer::~Reproducer() = default;
>
> ReproducerGenerate::ReproducerGenerate(std::error_code &EC)
> - : Root(createReproducerDir(EC)), FC() {
> + : Root(createReproducerDir(EC)) {
> if (!Root.empty())
> FC = std::make_shared<FileCollector>(Root, Root);
> VFS = FileCollector::createCollectorVFS(vfs::getRealFileSystem(), FC);
>
> diff --git a/llvm/tools/llvm-cov/CoverageSummaryInfo.h
> b/llvm/tools/llvm-cov/CoverageSummaryInfo.h
> index 62e7cad1012b1..84a3228f22b9a 100644
> --- a/llvm/tools/llvm-cov/CoverageSummaryInfo.h
> +++ b/llvm/tools/llvm-cov/CoverageSummaryInfo.h
> @@ -191,8 +191,7 @@ struct FunctionCoverageSummary {
> BranchCoverageInfo BranchCoverage;
>
> FunctionCoverageSummary(const std::string &Name)
> - : Name(Name), ExecutionCount(0), RegionCoverage(), LineCoverage(),
> - BranchCoverage() {}
> + : Name(Name), ExecutionCount(0) {}
>
> FunctionCoverageSummary(const std::string &Name, uint64_t
> ExecutionCount,
> const RegionCoverageInfo &RegionCoverage,
> @@ -223,9 +222,7 @@ struct FileCoverageSummary {
> FunctionCoverageInfo FunctionCoverage;
> FunctionCoverageInfo InstantiationCoverage;
>
> - FileCoverageSummary(StringRef Name)
> - : Name(Name), RegionCoverage(), LineCoverage(), FunctionCoverage(),
> - InstantiationCoverage() {}
> + FileCoverageSummary(StringRef Name) : Name(Name) {}
>
> FileCoverageSummary &operator+=(const FileCoverageSummary &RHS) {
> RegionCoverage += RHS.RegionCoverage;
>
> diff --git a/llvm/tools/llvm-mca/CodeRegion.h
> b/llvm/tools/llvm-mca/CodeRegion.h
> index 0b2590767dfab..0e1e02a533d80 100644
> --- a/llvm/tools/llvm-mca/CodeRegion.h
> +++ b/llvm/tools/llvm-mca/CodeRegion.h
> @@ -63,7 +63,7 @@ class CodeRegion {
>
> public:
> CodeRegion(llvm::StringRef Desc, llvm::SMLoc Start)
> - : Description(Desc), RangeStart(Start), RangeEnd() {}
> + : Description(Desc), RangeStart(Start) {}
>
> void addInstruction(const llvm::MCInst &Instruction) {
> Instructions.emplace_back(Instruction);
>
> diff --git a/llvm/tools/llvm-mca/PipelinePrinter.h
> b/llvm/tools/llvm-mca/PipelinePrinter.h
> index fd262f0a8a5d5..d89e913f979f6 100644
> --- a/llvm/tools/llvm-mca/PipelinePrinter.h
> +++ b/llvm/tools/llvm-mca/PipelinePrinter.h
> @@ -53,7 +53,7 @@ class PipelinePrinter {
> public:
> PipelinePrinter(Pipeline &Pipe, const CodeRegion &R, unsigned Idx,
> const MCSubtargetInfo &STI, const PipelineOptions &PO)
> - : P(Pipe), Region(R), RegionIdx(Idx), STI(STI), PO(PO), Views() {}
> + : P(Pipe), Region(R), RegionIdx(Idx), STI(STI), PO(PO) {}
>
> void addView(std::unique_ptr<View> V) {
> P.addEventListener(V.get());
>
> diff --git a/llvm/tools/llvm-objcopy/ELF/Object.h
> b/llvm/tools/llvm-objcopy/ELF/Object.h
> index 439380fc725b3..681ab8f56381c 100644
> --- a/llvm/tools/llvm-objcopy/ELF/Object.h
> +++ b/llvm/tools/llvm-objcopy/ELF/Object.h
> @@ -934,8 +934,7 @@ class BinaryELFBuilder : public BasicELFBuilder {
>
> public:
> BinaryELFBuilder(MemoryBuffer *MB, uint8_t NewSymbolVisibility)
> - : BasicELFBuilder(), MemBuf(MB),
> - NewSymbolVisibility(NewSymbolVisibility) {}
> + : MemBuf(MB), NewSymbolVisibility(NewSymbolVisibility) {}
>
> Expected<std::unique_ptr<Object>> build();
> };
> @@ -946,8 +945,7 @@ class IHexELFBuilder : public BasicELFBuilder {
> void addDataSections();
>
> public:
> - IHexELFBuilder(const std::vector<IHexRecord> &Records)
> - : BasicELFBuilder(), Records(Records) {}
> + IHexELFBuilder(const std::vector<IHexRecord> &Records) :
> Records(Records) {}
>
> Expected<std::unique_ptr<Object>> build();
> };
>
> diff --git a/llvm/tools/llvm-objdump/SourcePrinter.h
> b/llvm/tools/llvm-objdump/SourcePrinter.h
> index 21d5bdcf8a49d..31d46e3108f68 100644
> --- a/llvm/tools/llvm-objdump/SourcePrinter.h
> +++ b/llvm/tools/llvm-objdump/SourcePrinter.h
> @@ -80,7 +80,7 @@ class LiveVariablePrinter {
>
> public:
> LiveVariablePrinter(const MCRegisterInfo &MRI, const MCSubtargetInfo
> &STI)
> - : LiveVariables(), ActiveCols(Column()), MRI(MRI), STI(STI) {}
> + : ActiveCols(Column()), MRI(MRI), STI(STI) {}
>
> void dump() const;
>
>
> diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp
> b/llvm/tools/llvm-profdata/llvm-profdata.cpp
> index 6c12750a9ddf1..0d7eabd6d1584 100644
> --- a/llvm/tools/llvm-profdata/llvm-profdata.cpp
> +++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp
> @@ -204,8 +204,8 @@ struct WriterContext {
>
> WriterContext(bool IsSparse, std::mutex &ErrLock,
> SmallSet<instrprof_error, 4> &WriterErrorCodes)
> - : Lock(), Writer(IsSparse), Errors(), ErrLock(ErrLock),
> - WriterErrorCodes(WriterErrorCodes) {}
> + : Writer(IsSparse), ErrLock(ErrLock),
> WriterErrorCodes(WriterErrorCodes) {
> + }
> };
>
> /// Computer the overlap b/w profile BaseFilename and TestFileName,
> @@ -2303,8 +2303,7 @@ struct HotFuncInfo {
> uint64_t EntryCount;
>
> HotFuncInfo()
> - : FuncName(), TotalCount(0), TotalCountPercent(0.0f), MaxCount(0),
> - EntryCount(0) {}
> + : TotalCount(0), TotalCountPercent(0.0f), MaxCount(0),
> EntryCount(0) {}
>
> HotFuncInfo(StringRef FN, uint64_t TS, double TSP, uint64_t MS,
> uint64_t ES)
> : FuncName(FN.begin(), FN.end()), TotalCount(TS),
> TotalCountPercent(TSP),
>
> diff --git a/llvm/tools/llvm-readobj/llvm-readobj.cpp
> b/llvm/tools/llvm-readobj/llvm-readobj.cpp
> index 46862bbad7cb6..eea486abe0a10 100644
> --- a/llvm/tools/llvm-readobj/llvm-readobj.cpp
> +++ b/llvm/tools/llvm-readobj/llvm-readobj.cpp
> @@ -286,8 +286,8 @@ static void parseOptions(const opt::InputArgList
> &Args) {
> namespace {
> struct ReadObjTypeTableBuilder {
> ReadObjTypeTableBuilder()
> - : Allocator(), IDTable(Allocator), TypeTable(Allocator),
> - GlobalIDTable(Allocator), GlobalTypeTable(Allocator) {}
> + : IDTable(Allocator), TypeTable(Allocator),
> GlobalIDTable(Allocator),
> + GlobalTypeTable(Allocator) {}
>
> llvm::BumpPtrAllocator Allocator;
> llvm::codeview::MergingTypeTableBuilder IDTable;
>
> diff --git a/llvm/utils/TableGen/GlobalISel/GIMatchDag.h
> b/llvm/utils/TableGen/GlobalISel/GIMatchDag.h
> index 5675805408779..37570648cad17 100644
> --- a/llvm/utils/TableGen/GlobalISel/GIMatchDag.h
> +++ b/llvm/utils/TableGen/GlobalISel/GIMatchDag.h
> @@ -84,9 +84,7 @@ class GIMatchDag {
> bool HasPostMatchPredicate = false;
>
> public:
> - GIMatchDag(GIMatchDagContext &Ctx)
> - : Ctx(Ctx), InstrNodes(), PredicateNodes(), Edges(),
> - PredicateDependencies() {}
> + GIMatchDag(GIMatchDagContext &Ctx) : Ctx(Ctx) {}
> GIMatchDag(const GIMatchDag &) = delete;
>
> GIMatchDagContext &getContext() const { return Ctx; }
>
> diff --git a/llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp
> b/llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp
> index d08a83333c305..00d57404b0698 100644
> --- a/llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp
> +++ b/llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp
> @@ -82,7 +82,6 @@ GIMatchTreeBuilderLeafInfo::GIMatchTreeBuilderLeafInfo(
> GIMatchTreeBuilder &Builder, StringRef Name, unsigned RootIdx,
> const GIMatchDag &MatchDag, void *Data)
> : Builder(Builder), Info(Name, RootIdx, Data), MatchDag(MatchDag),
> - InstrNodeToInfo(),
> RemainingInstrNodes(BitVector(MatchDag.getNumInstrNodes(), true)),
> RemainingEdges(BitVector(MatchDag.getNumEdges(), true)),
> RemainingPredicates(BitVector(MatchDag.getNumPredicates(), true)),
>
> diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp
> b/llvm/utils/TableGen/GlobalISelEmitter.cpp
> index 7b1bd41a951bb..25bc0adc2a813 100644
> --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
> +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
> @@ -883,9 +883,7 @@ class RuleMatcher : public Matcher {
>
> public:
> RuleMatcher(ArrayRef<SMLoc> SrcLoc)
> - : Matchers(), Actions(), InsnVariableIDs(), MutatableInsns(),
> - DefinedOperands(), NextInsnVarID(0), NextOutputInsnID(0),
> - NextTempRegID(0), SrcLoc(SrcLoc), ComplexSubOperands(),
> + : NextInsnVarID(0), NextOutputInsnID(0), NextTempRegID(0),
> SrcLoc(SrcLoc),
> RuleID(NextRuleID++) {}
> RuleMatcher(RuleMatcher &&Other) = default;
> RuleMatcher &operator=(RuleMatcher &&Other) = default;
>
> diff --git a/llvm/utils/TableGen/PredicateExpander.h
> b/llvm/utils/TableGen/PredicateExpander.h
> index 29cca92d902ce..9e7a4a3925acf 100644
> --- a/llvm/utils/TableGen/PredicateExpander.h
> +++ b/llvm/utils/TableGen/PredicateExpander.h
> @@ -111,7 +111,7 @@ class STIPredicateExpander : public PredicateExpander {
>
> public:
> STIPredicateExpander(StringRef Target)
> - : PredicateExpander(Target), ClassPrefix(), ExpandDefinition(false)
> {}
> + : PredicateExpander(Target), ExpandDefinition(false) {}
>
> bool shouldExpandDefinition() const { return ExpandDefinition; }
> StringRef getClassPrefix() const { return ClassPrefix; }
>
> diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp
> b/llvm/utils/TableGen/RegisterBankEmitter.cpp
> index 0725657150f85..61f71309b6fb2 100644
> --- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
> +++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
> @@ -42,7 +42,7 @@ class RegisterBank {
>
> public:
> RegisterBank(const Record &TheDef)
> - : TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}
> + : TheDef(TheDef), RCWithLargestRegsSize(nullptr) {}
>
> /// Get the human-readable name for the bank.
> StringRef getName() const { return TheDef.getValueAsString("Name"); }
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits
>
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