<div dir="ltr">This is causing lots of warnings from gcc on my machine. For example<div><br></div><div>
<p class="gmail-p1" style="margin:0px;font-variant-numeric:normal;font-variant-east-asian:normal;font-stretch:normal;font-size:11px;line-height:normal;font-family:Menlo;color:rgb(0,0,0)"><span class="gmail-s1" style="font-variant-ligatures:no-common-ligatures"><b>llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:</b> In copy constructor ‘<b>{anonymous}::RISCVOperand::RISCVOperand(const {anonymous}::RISCVOperand&)</b>’:</span></p>
<p class="gmail-p1" style="margin:0px;font-variant-numeric:normal;font-variant-east-asian:normal;font-stretch:normal;font-size:11px;line-height:normal;font-family:Menlo;color:rgb(0,0,0)"><span class="gmail-s1" style="font-variant-ligatures:no-common-ligatures"><b>llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:308:3:</b> </span><span class="gmail-s2" style="font-variant-ligatures:no-common-ligatures;color:rgb(219,39,218)"><b>warning: </b></span><span class="gmail-s1" style="font-variant-ligatures:no-common-ligatures">base class ‘<b>class llvm::MCParsedAsmOperand</b>’ should be explicitly initialized in the copy constructor [</span><span class="gmail-s2" style="font-variant-ligatures:no-common-ligatures;color:rgb(219,39,218)"><b>-Wextra</b></span><span class="gmail-s1" style="font-variant-ligatures:no-common-ligatures">]</span></p>
<p class="gmail-p1" style="margin:0px;font-variant-numeric:normal;font-variant-east-asian:normal;font-stretch:normal;font-size:11px;line-height:normal;font-family:Menlo;color:rgb(0,0,0)"><span class="gmail-s1" style="font-variant-ligatures:no-common-ligatures"><span class="gmail-Apple-converted-space">Â Â </span></span><span class="gmail-s2" style="font-variant-ligatures:no-common-ligatures;color:rgb(219,39,218)"><b>RISCVOperand</b></span><span class="gmail-s1" style="font-variant-ligatures:no-common-ligatures">(const RISCVOperand &o) {</span></p>
<p class="gmail-p2" style="margin:0px;font-variant-numeric:normal;font-variant-east-asian:normal;font-stretch:normal;font-size:11px;line-height:normal;font-family:Menlo;color:rgb(219,39,218)"><span class="gmail-s3" style="font-variant-ligatures:no-common-ligatures;color:rgb(0,0,0)"><span class="gmail-Apple-converted-space">Â Â </span></span><span class="gmail-s1" style="font-variant-ligatures:no-common-ligatures"><b>^~~~~~~~~~~~</b></span></p><div><div><br clear="all"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature">~Craig</div></div><br></div></div></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sat, Jan 1, 2022 at 4:18 PM Kazu Hirata via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Kazu Hirata<br>
Date: 2022-01-01T16:18:18-08:00<br>
New Revision: fd4808887ee47f3ec8a030e9211169ef4fb094c3<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/fd4808887ee47f3ec8a030e9211169ef4fb094c3" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/fd4808887ee47f3ec8a030e9211169ef4fb094c3</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/fd4808887ee47f3ec8a030e9211169ef4fb094c3.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/fd4808887ee47f3ec8a030e9211169ef4fb094c3.diff</a><br>
<br>
LOG: [llvm] Remove redundant member initialization (NFC)<br>
<br>
Identified with readability-redundant-member-init.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
  llvm/include/llvm/ADT/Triple.h<br>
  llvm/include/llvm/Analysis/BasicAliasAnalysis.h<br>
  llvm/include/llvm/Analysis/DDG.h<br>
  llvm/include/llvm/Analysis/LazyCallGraph.h<br>
  llvm/include/llvm/Analysis/MemoryLocation.h<br>
  llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h<br>
  llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h<br>
  llvm/include/llvm/CodeGen/CodeGenPassBuilder.h<br>
  llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h<br>
  llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h<br>
  llvm/include/llvm/CodeGen/MachinePassManager.h<br>
  llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h<br>
  llvm/include/llvm/DWARFLinker/DWARFLinker.h<br>
  llvm/include/llvm/DebugInfo/GSYM/StringTable.h<br>
  llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h<br>
  llvm/include/llvm/FileCheck/FileCheck.h<br>
  llvm/include/llvm/IR/LegacyPassManagers.h<br>
  llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h<br>
  llvm/include/llvm/MCA/HardwareUnits/LSUnit.h<br>
  llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h<br>
  llvm/include/llvm/MCA/Stages/EntryStage.h<br>
  llvm/include/llvm/MCA/Stages/ExecuteStage.h<br>
  llvm/include/llvm/MCA/Stages/InOrderIssueStage.h<br>
  llvm/include/llvm/MCA/Stages/InstructionTables.h<br>
  llvm/include/llvm/MCA/Stages/RetireStage.h<br>
  llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h<br>
  llvm/include/llvm/Remarks/RemarkSerializer.h<br>
  llvm/include/llvm/Support/ScopedPrinter.h<br>
  llvm/include/llvm/Transforms/IPO/Attributor.h<br>
  llvm/include/llvm/Transforms/Scalar/LoopPassManager.h<br>
  llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp<br>
  llvm/lib/Analysis/CallGraphSCCPass.cpp<br>
  llvm/lib/Analysis/DDG.cpp<br>
  llvm/lib/Analysis/GlobalsModRef.cpp<br>
  llvm/lib/Analysis/IVUsers.cpp<br>
  llvm/lib/Analysis/LoopCacheAnalysis.cpp<br>
  llvm/lib/Analysis/LoopPass.cpp<br>
  llvm/lib/Analysis/RegionPass.cpp<br>
  llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp<br>
  llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp<br>
  llvm/lib/CodeGen/MIRParser/MIRParser.cpp<br>
  llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp<br>
  llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp<br>
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp<br>
  llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp<br>
  llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp<br>
  llvm/lib/IR/LegacyPassManager.cpp<br>
  llvm/lib/IR/Module.cpp<br>
  llvm/lib/InterfaceStub/IFSStub.cpp<br>
  llvm/lib/MC/MCParser/AsmParser.cpp<br>
  llvm/lib/MC/MCParser/MasmParser.cpp<br>
  llvm/lib/MCA/Stages/DispatchStage.cpp<br>
  llvm/lib/MCA/Stages/InOrderIssueStage.cpp<br>
  llvm/lib/Remarks/BitstreamRemarkSerializer.cpp<br>
  llvm/lib/Remarks/RemarkStreamer.cpp<br>
  llvm/lib/Remarks/RemarkStringTable.cpp<br>
  llvm/lib/Remarks/YAMLRemarkParser.cpp<br>
  llvm/lib/Support/YAMLParser.cpp<br>
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp<br>
  llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp<br>
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp<br>
  llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h<br>
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp<br>
  llvm/lib/Target/AMDGPU/AMDGPULibFunc.h<br>
  llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp<br>
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp<br>
  llvm/lib/Target/ARM/ARMHazardRecognizer.cpp<br>
  llvm/lib/Target/ARM/ARMHazardRecognizer.h<br>
  llvm/lib/Target/ARM/ARMInstrInfo.cpp<br>
  llvm/lib/Target/ARM/ARMInstructionSelector.cpp<br>
  llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp<br>
  llvm/lib/Target/ARM/ARMRegisterInfo.cpp<br>
  llvm/lib/Target/ARM/ARMTargetObjectFile.h<br>
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
  llvm/lib/Target/ARM/Thumb1InstrInfo.cpp<br>
  llvm/lib/Target/ARM/ThumbRegisterInfo.cpp<br>
  llvm/lib/Target/AVR/AVRSubtarget.cpp<br>
  llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp<br>
  llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp<br>
  llvm/lib/Target/BPF/BPFSubtarget.cpp<br>
  llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
  llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
  llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp<br>
  llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp<br>
  llvm/lib/Target/Lanai/LanaiSubtarget.cpp<br>
  llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp<br>
  llvm/lib/Target/MSP430/MSP430Subtarget.cpp<br>
  llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp<br>
  llvm/lib/Target/Mips/Mips16RegisterInfo.cpp<br>
  llvm/lib/Target/Mips/MipsInstructionSelector.cpp<br>
  llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp<br>
  llvm/lib/Target/Mips/MipsSERegisterInfo.cpp<br>
  llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp<br>
  llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp<br>
  llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h<br>
  llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp<br>
  llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp<br>
  llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp<br>
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp<br>
  llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp<br>
  llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp<br>
  llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp<br>
  llvm/lib/Target/Sparc/SparcTargetObjectFile.h<br>
  llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp<br>
  llvm/lib/Target/SystemZ/SystemZSubtarget.cpp<br>
  llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp<br>
  llvm/lib/Target/VE/VEMachineFunctionInfo.h<br>
  llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp<br>
  llvm/lib/Target/X86/X86ISelDAGToDAG.cpp<br>
  llvm/lib/Target/X86/X86InstructionSelector.cpp<br>
  llvm/lib/Target/X86/X86RegisterBankInfo.cpp<br>
  llvm/lib/Target/XCore/XCoreSubtarget.cpp<br>
  llvm/lib/Transforms/IPO/Inliner.cpp<br>
  llvm/lib/Transforms/IPO/PartialInlining.cpp<br>
  llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp<br>
  llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp<br>
  llvm/lib/Transforms/Vectorize/VPlan.h<br>
  llvm/tools/dsymutil/BinaryHolder.h<br>
  llvm/tools/dsymutil/Reproducer.cpp<br>
  llvm/tools/llvm-cov/CoverageSummaryInfo.h<br>
  llvm/tools/llvm-mca/CodeRegion.h<br>
  llvm/tools/llvm-mca/PipelinePrinter.h<br>
  llvm/tools/llvm-objcopy/ELF/Object.h<br>
  llvm/tools/llvm-objdump/SourcePrinter.h<br>
  llvm/tools/llvm-profdata/llvm-profdata.cpp<br>
  llvm/tools/llvm-readobj/llvm-readobj.cpp<br>
  llvm/utils/TableGen/GlobalISel/GIMatchDag.h<br>
  llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp<br>
  llvm/utils/TableGen/GlobalISelEmitter.cpp<br>
  llvm/utils/TableGen/PredicateExpander.h<br>
  llvm/utils/TableGen/RegisterBankEmitter.cpp<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h<br>
index 6f1f1618fbc27..45a8b8d927140 100644<br>
--- a/llvm/include/llvm/ADT/Triple.h<br>
+++ b/llvm/include/llvm/ADT/Triple.h<br>
@@ -271,9 +271,7 @@ class Triple {<br>
<br>
  /// Default constructor is the same as an empty string and leaves all<br>
  /// triple fields unknown.<br>
-Â Triple()<br>
-Â Â Â : Data(), Arch(), SubArch(), Vendor(), OS(), Environment(),<br>
-Â Â Â Â ObjectFormat() {}<br>
+Â Triple() : Arch(), SubArch(), Vendor(), OS(), Environment(), ObjectFormat() {}<br>
<br>
  explicit Triple(const Twine &Str);<br>
  Triple(const Twine &ArchStr, const Twine &VendorStr, const Twine &OSStr);<br>
<br>
diff --git a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h<br>
index ed9d1ba4c5a75..361765d852574 100644<br>
--- a/llvm/include/llvm/Analysis/BasicAliasAnalysis.h<br>
+++ b/llvm/include/llvm/Analysis/BasicAliasAnalysis.h<br>
@@ -58,7 +58,7 @@ class BasicAAResult : public AAResultBase<BasicAAResult> {<br>
  BasicAAResult(const DataLayout &DL, const Function &F,<br>
         const TargetLibraryInfo &TLI, AssumptionCache &AC,<br>
         DominatorTree *DT = nullptr, PhiValues *PV = nullptr)<br>
-Â Â Â : AAResultBase(), DL(DL), F(F), TLI(TLI), AC(AC), DT(DT), PV(PV) {}<br>
+Â Â Â : DL(DL), F(F), TLI(TLI), AC(AC), DT(DT), PV(PV) {}<br>
<br>
  BasicAAResult(const BasicAAResult &Arg)<br>
    : AAResultBase(Arg), DL(Arg.DL), F(Arg.F), TLI(Arg.TLI), AC(Arg.AC),<br>
<br>
diff --git a/llvm/include/llvm/Analysis/DDG.h b/llvm/include/llvm/Analysis/DDG.h<br>
index 51dd4a738f00b..4ea589ec7efc8 100644<br>
--- a/llvm/include/llvm/Analysis/DDG.h<br>
+++ b/llvm/include/llvm/Analysis/DDG.h<br>
@@ -52,7 +52,7 @@ class DDGNode : public DDGNodeBase {<br>
  };<br>
<br>
  DDGNode() = delete;<br>
-Â DDGNode(const NodeKind K) : DDGNodeBase(), Kind(K) {}<br>
+Â DDGNode(const NodeKind K) : Kind(K) {}<br>
  DDGNode(const DDGNode &N) : DDGNodeBase(N), Kind(N.Kind) {}<br>
  DDGNode(DDGNode &&N) : DDGNodeBase(std::move(N)), Kind(N.Kind) {}<br>
  virtual ~DDGNode() = 0;<br>
<br>
diff --git a/llvm/include/llvm/Analysis/LazyCallGraph.h b/llvm/include/llvm/Analysis/LazyCallGraph.h<br>
index 0580f4d7b226c..5828274cc02bc 100644<br>
--- a/llvm/include/llvm/Analysis/LazyCallGraph.h<br>
+++ b/llvm/include/llvm/Analysis/LazyCallGraph.h<br>
@@ -1190,7 +1190,7 @@ class LazyCallGraph {<br>
  }<br>
 };<br>
<br>
-inline LazyCallGraph::Edge::Edge() : Value() {}<br>
+inline LazyCallGraph::Edge::Edge() {}<br>
 inline LazyCallGraph::Edge::Edge(Node &N, Kind K) : Value(&N, K) {}<br>
<br>
 inline LazyCallGraph::Edge::operator bool() const {<br>
<br>
diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h b/llvm/include/llvm/Analysis/MemoryLocation.h<br>
index 833fce1b17265..23e50f601e042 100644<br>
--- a/llvm/include/llvm/Analysis/MemoryLocation.h<br>
+++ b/llvm/include/llvm/Analysis/MemoryLocation.h<br>
@@ -284,8 +284,7 @@ class MemoryLocation {<br>
   return T.isScalable() ? UnknownSize : T.getFixedSize();<br>
  }<br>
<br>
-Â MemoryLocation()<br>
-Â Â Â : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()), AATags() {}<br>
+Â MemoryLocation() : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()) {}<br>
<br>
  explicit MemoryLocation(const Value *Ptr, LocationSize Size,<br>
              const AAMDNodes &AATags = AAMDNodes())<br>
<br>
diff --git a/llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h b/llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h<br>
index b4f4e5f29768b..d19a6394bd486 100644<br>
--- a/llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h<br>
+++ b/llvm/include/llvm/Analysis/ObjCARCAliasAnalysis.h<br>
@@ -40,7 +40,7 @@ class ObjCARCAAResult : public AAResultBase<ObjCARCAAResult> {<br>
  const DataLayout &DL;<br>
<br>
 public:<br>
-Â explicit ObjCARCAAResult(const DataLayout &DL) : AAResultBase(), DL(DL) {}<br>
+Â explicit ObjCARCAAResult(const DataLayout &DL) : DL(DL) {}<br>
  ObjCARCAAResult(ObjCARCAAResult &&Arg)<br>
    : AAResultBase(std::move(Arg)), DL(Arg.DL) {}<br>
<br>
<br>
diff --git a/llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h b/llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h<br>
index 20acb407ead00..ebd427354cee9 100644<br>
--- a/llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h<br>
+++ b/llvm/include/llvm/Analysis/ScalarEvolutionAliasAnalysis.h<br>
@@ -27,7 +27,7 @@ class SCEVAAResult : public AAResultBase<SCEVAAResult> {<br>
  ScalarEvolution &SE;<br>
<br>
 public:<br>
-Â explicit SCEVAAResult(ScalarEvolution &SE) : AAResultBase(), SE(SE) {}<br>
+Â explicit SCEVAAResult(ScalarEvolution &SE) : SE(SE) {}<br>
  SCEVAAResult(SCEVAAResult &&Arg) : AAResultBase(std::move(Arg)), SE(Arg.SE) {}<br>
<br>
  AliasResult alias(const MemoryLocation &LocA, const MemoryLocation &LocB,<br>
<br>
diff --git a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h<br>
index 1fd07ca2c8d42..f6563971f9812 100644<br>
--- a/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h<br>
+++ b/llvm/include/llvm/CodeGen/CodeGenPassBuilder.h<br>
@@ -159,7 +159,7 @@ template <typename DerivedT> class CodeGenPassBuilder {<br>
  class AddIRPass {<br>
  public:<br>
   AddIRPass(ModulePassManager &MPM, bool DebugPM, bool Check = true)<br>
-Â Â Â Â : MPM(MPM), FPM() {<br>
+Â Â Â Â : MPM(MPM) {<br>
    if (Check)<br>
     AddingFunctionPasses = false;<br>
   }<br>
<br>
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h<br>
index 9c878d4b087ba..82c125993ec3d 100644<br>
--- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h<br>
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h<br>
@@ -95,7 +95,7 @@ class CallLowering {<br>
       bool IsFixed = true)<br>
    : ArgInfo(Regs, OrigValue.getType(), OrigIndex, Flags, IsFixed, &OrigValue) {}<br>
<br>
-Â Â ArgInfo() : BaseArgInfo() {}<br>
+Â Â ArgInfo() {}<br>
  };<br>
<br>
  struct CallLoweringInfo {<br>
<br>
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h<br>
index a02b15639946d..9507c3411b5c8 100644<br>
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h<br>
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h<br>
@@ -556,7 +556,7 @@ class LegalizeRuleSet {<br>
  }<br>
<br>
 public:<br>
-Â LegalizeRuleSet() : AliasOf(0), IsAliasedByAnother(false), Rules() {}<br>
+Â LegalizeRuleSet() : AliasOf(0), IsAliasedByAnother(false) {}<br>
<br>
  bool isAliasedByAnother() { return IsAliasedByAnother; }<br>
  void setIsAliasedByAnother() { IsAliasedByAnother = true; }<br>
<br>
diff --git a/llvm/include/llvm/CodeGen/MachinePassManager.h b/llvm/include/llvm/CodeGen/MachinePassManager.h<br>
index f967167c65e13..75b8a89c812e9 100644<br>
--- a/llvm/include/llvm/CodeGen/MachinePassManager.h<br>
+++ b/llvm/include/llvm/CodeGen/MachinePassManager.h<br>
@@ -40,10 +40,10 @@ class MachineFunctionAnalysisManager : public AnalysisManager<MachineFunction> {<br>
 public:<br>
  using Base = AnalysisManager<MachineFunction>;<br>
<br>
-Â MachineFunctionAnalysisManager() : Base(), FAM(nullptr), MAM(nullptr) {}<br>
+Â MachineFunctionAnalysisManager() : FAM(nullptr), MAM(nullptr) {}<br>
  MachineFunctionAnalysisManager(FunctionAnalysisManager &FAM,<br>
                 ModuleAnalysisManager &MAM)<br>
-Â Â Â : Base(), FAM(&FAM), MAM(&MAM) {}<br>
+Â Â Â : FAM(&FAM), MAM(&MAM) {}<br>
  MachineFunctionAnalysisManager(MachineFunctionAnalysisManager &&) = default;<br>
  MachineFunctionAnalysisManager &<br>
  operator=(MachineFunctionAnalysisManager &&) = default;<br>
@@ -135,7 +135,7 @@ class MachineFunctionPassManager<br>
  MachineFunctionPassManager(bool DebugLogging = false,<br>
               bool RequireCodeGenSCCOrder = false,<br>
               bool VerifyMachineFunction = false)<br>
-Â Â Â : Base(), RequireCodeGenSCCOrder(RequireCodeGenSCCOrder),<br>
+Â Â Â : RequireCodeGenSCCOrder(RequireCodeGenSCCOrder),<br>
     VerifyMachineFunction(VerifyMachineFunction) {}<br>
  MachineFunctionPassManager(MachineFunctionPassManager &&) = default;<br>
  MachineFunctionPassManager &<br>
<br>
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h b/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h<br>
index 6a3d76be0ed63..0f3af915da649 100644<br>
--- a/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h<br>
+++ b/llvm/include/llvm/CodeGen/SelectionDAGAddressAnalysis.h<br>
@@ -39,7 +39,7 @@ class BaseIndexOffset {<br>
 public:<br>
  BaseIndexOffset() = default;<br>
  BaseIndexOffset(SDValue Base, SDValue Index, bool IsIndexSignExt)<br>
-Â Â Â : Base(Base), Index(Index), Offset(), IsIndexSignExt(IsIndexSignExt) {}<br>
+Â Â Â : Base(Base), Index(Index), IsIndexSignExt(IsIndexSignExt) {}<br>
  BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,<br>
          bool IsIndexSignExt)<br>
    : Base(Base), Index(Index), Offset(Offset),<br>
<br>
diff --git a/llvm/include/llvm/DWARFLinker/DWARFLinker.h b/llvm/include/llvm/DWARFLinker/DWARFLinker.h<br>
index 1c6d0b1ead86b..4f1c666df35fa 100644<br>
--- a/llvm/include/llvm/DWARFLinker/DWARFLinker.h<br>
+++ b/llvm/include/llvm/DWARFLinker/DWARFLinker.h<br>
@@ -385,8 +385,8 @@ class DWARFLinker {<br>
     : Die(Die), Type(T), CU(CU), Flags(0), OtherInfo(OtherInfo) {}<br>
<br>
   WorklistItem(unsigned AncestorIdx, CompileUnit &CU, unsigned Flags)<br>
-Â Â Â Â : Die(), Type(WorklistItemType::LookForParentDIEsToKeep), CU(CU),<br>
-Â Â Â Â Â Flags(Flags), AncestorIdx(AncestorIdx) {}<br>
+Â Â Â Â : Type(WorklistItemType::LookForParentDIEsToKeep), CU(CU), Flags(Flags),<br>
+Â Â Â Â Â AncestorIdx(AncestorIdx) {}<br>
  };<br>
<br>
  /// returns true if we need to translate strings.<br>
<br>
diff --git a/llvm/include/llvm/DebugInfo/GSYM/StringTable.h b/llvm/include/llvm/DebugInfo/GSYM/StringTable.h<br>
index 045c9e3f3ebd2..6dd90499c203a 100644<br>
--- a/llvm/include/llvm/DebugInfo/GSYM/StringTable.h<br>
+++ b/llvm/include/llvm/DebugInfo/GSYM/StringTable.h<br>
@@ -20,7 +20,7 @@ namespace gsym {<br>
 /// string at offset zero. Strings must be UTF8 NULL terminated strings.<br>
 struct StringTable {<br>
  StringRef Data;<br>
-Â StringTable() : Data() {}<br>
+Â StringTable() {}<br>
  StringTable(StringRef D) : Data(D) {}<br>
  StringRef operator[](size_t Offset) const { return getString(Offset); }<br>
  StringRef getString(uint32_t Offset) const {<br>
<br>
diff --git a/llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h b/llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h<br>
index 4bb11bf62593a..779dc885372d6 100644<br>
--- a/llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h<br>
+++ b/llvm/include/llvm/DebugInfo/Symbolize/DIPrinter.h<br>
@@ -87,7 +87,7 @@ class PlainPrinterBase : public DIPrinter {<br>
<br>
 public:<br>
  PlainPrinterBase(raw_ostream &OS, raw_ostream &ES, PrinterConfig &Config)<br>
-Â Â Â : DIPrinter(), OS(OS), ES(ES), Config(Config) {}<br>
+Â Â Â : OS(OS), ES(ES), Config(Config) {}<br>
<br>
  void print(const Request &Request, const DILineInfo &Info) override;<br>
  void print(const Request &Request, const DIInliningInfo &Info) override;<br>
@@ -138,7 +138,7 @@ class JSONPrinter : public DIPrinter {<br>
<br>
 public:<br>
  JSONPrinter(raw_ostream &OS, PrinterConfig &Config)<br>
-Â Â Â : DIPrinter(), OS(OS), Config(Config) {}<br>
+Â Â Â : OS(OS), Config(Config) {}<br>
<br>
  void print(const Request &Request, const DILineInfo &Info) override;<br>
  void print(const Request &Request, const DIInliningInfo &Info) override;<br>
<br>
diff --git a/llvm/include/llvm/FileCheck/FileCheck.h b/llvm/include/llvm/FileCheck/FileCheck.h<br>
index 6ed75e14ccb65..7a6c98db3029b 100644<br>
--- a/llvm/include/llvm/FileCheck/FileCheck.h<br>
+++ b/llvm/include/llvm/FileCheck/FileCheck.h<br>
@@ -80,8 +80,7 @@ class FileCheckType {<br>
  std::bitset<FileCheckKindModifier::Size> Modifiers;<br>
<br>
 public:<br>
-Â FileCheckType(FileCheckKind Kind = CheckNone)<br>
-Â Â Â : Kind(Kind), Count(1), Modifiers() {}<br>
+Â FileCheckType(FileCheckKind Kind = CheckNone) : Kind(Kind), Count(1) {}<br>
  FileCheckType(const FileCheckType &) = default;<br>
  FileCheckType &operator=(const FileCheckType &) = default;<br>
<br>
<br>
diff --git a/llvm/include/llvm/IR/LegacyPassManagers.h b/llvm/include/llvm/IR/LegacyPassManagers.h<br>
index 0bcb408d49292..e161bdee961a4 100644<br>
--- a/llvm/include/llvm/IR/LegacyPassManagers.h<br>
+++ b/llvm/include/llvm/IR/LegacyPassManagers.h<br>
@@ -460,8 +460,7 @@ class PMDataManager {<br>
 class FPPassManager : public ModulePass, public PMDataManager {<br>
 public:<br>
  static char ID;<br>
-Â explicit FPPassManager()<br>
-Â : ModulePass(ID), PMDataManager() { }<br>
+Â explicit FPPassManager() : ModulePass(ID) {}<br>
<br>
  /// run - Execute all of the passes scheduled for execution. Keep track of<br>
  /// whether any of the passes modifies the module, and if so, return true.<br>
<br>
diff --git a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h<br>
index 908ee30e40609..2f57b85a92321 100644<br>
--- a/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h<br>
+++ b/llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h<br>
@@ -68,9 +68,7 @@ struct IntelExpr {<br>
  StringRef OffsetName;<br>
  unsigned Scale;<br>
<br>
-Â IntelExpr()<br>
-Â Â Â : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()),<br>
-Â Â Â Â OffsetName(StringRef()), Scale(1) {}<br>
+Â IntelExpr() : NeedBracs(false), Imm(0), Scale(1) {}<br>
  // [BaseReg + IndexReg * ScaleExpression + OFFSET name + ImmediateExpression]<br>
  IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale,<br>
       StringRef offsetName, int64_t imm, bool needBracs)<br>
<br>
diff --git a/llvm/include/llvm/MCA/HardwareUnits/LSUnit.h b/llvm/include/llvm/MCA/HardwareUnits/LSUnit.h<br>
index 7eddd067aa0cc..c05f770df8ebe 100644<br>
--- a/llvm/include/llvm/MCA/HardwareUnits/LSUnit.h<br>
+++ b/llvm/include/llvm/MCA/HardwareUnits/LSUnit.h<br>
@@ -55,7 +55,7 @@ class MemoryGroup {<br>
  MemoryGroup()<br>
    : NumPredecessors(0), NumExecutingPredecessors(0),<br>
     NumExecutedPredecessors(0), NumInstructions(0), NumExecuting(0),<br>
-Â Â Â Â NumExecuted(0), CriticalPredecessor(), CriticalMemoryInstruction() {}<br>
+Â Â Â Â NumExecuted(0), CriticalPredecessor() {}<br>
  MemoryGroup(MemoryGroup &&) = default;<br>
<br>
  size_t getNumSuccessors() const {<br>
<br>
diff --git a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h<br>
index b679b0d7d5373..7467fd6754f0c 100644<br>
--- a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h<br>
+++ b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h<br>
@@ -118,8 +118,8 @@ class DefaultResourceStrategy final : public ResourceStrategy {<br>
<br>
 public:<br>
  DefaultResourceStrategy(uint64_t UnitMask)<br>
-Â Â Â : ResourceStrategy(), ResourceUnitMask(UnitMask),<br>
-Â Â Â Â NextInSequenceMask(UnitMask), RemovedFromNextInSequence(0) {}<br>
+Â Â Â : ResourceUnitMask(UnitMask), NextInSequenceMask(UnitMask),<br>
+Â Â Â Â RemovedFromNextInSequence(0) {}<br>
  virtual ~DefaultResourceStrategy() = default;<br>
<br>
  uint64_t select(uint64_t ReadyMask) override;<br>
<br>
diff --git a/llvm/include/llvm/MCA/Stages/EntryStage.h b/llvm/include/llvm/MCA/Stages/EntryStage.h<br>
index 1c133898d603e..4c50838bef4b1 100644<br>
--- a/llvm/include/llvm/MCA/Stages/EntryStage.h<br>
+++ b/llvm/include/llvm/MCA/Stages/EntryStage.h<br>
@@ -36,7 +36,7 @@ class EntryStage final : public Stage {<br>
  EntryStage &operator=(const EntryStage &Other) = delete;<br>
<br>
 public:<br>
-Â EntryStage(SourceMgr &SM) : CurrentInstruction(), SM(SM), NumRetired(0) { }<br>
+Â EntryStage(SourceMgr &SM) : SM(SM), NumRetired(0) {}<br>
<br>
  bool isAvailable(const InstRef &IR) const override;<br>
  bool hasWorkToComplete() const override;<br>
<br>
diff --git a/llvm/include/llvm/MCA/Stages/ExecuteStage.h b/llvm/include/llvm/MCA/Stages/ExecuteStage.h<br>
index 4c09ca8255ff6..03a78a8b6b85b 100644<br>
--- a/llvm/include/llvm/MCA/Stages/ExecuteStage.h<br>
+++ b/llvm/include/llvm/MCA/Stages/ExecuteStage.h<br>
@@ -49,7 +49,7 @@ class ExecuteStage final : public Stage {<br>
 public:<br>
  ExecuteStage(Scheduler &S) : ExecuteStage(S, false) {}<br>
  ExecuteStage(Scheduler &S, bool ShouldPerformBottleneckAnalysis)<br>
-Â Â Â : Stage(), HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0),<br>
+Â Â Â : HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0),<br>
     EnablePressureEvents(ShouldPerformBottleneckAnalysis) {}<br>
<br>
  // This stage works under the assumption that the Pipeline will eventually<br>
<br>
diff --git a/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h b/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h<br>
index 42f386a13d85f..40bc3b5aed949 100644<br>
--- a/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h<br>
+++ b/llvm/include/llvm/MCA/Stages/InOrderIssueStage.h<br>
@@ -38,7 +38,7 @@ struct StallInfo {<br>
  unsigned CyclesLeft;<br>
  StallKind Kind;<br>
<br>
-Â StallInfo() : IR(), CyclesLeft(), Kind(StallKind::DEFAULT) {}<br>
+Â StallInfo() : CyclesLeft(), Kind(StallKind::DEFAULT) {}<br>
<br>
  StallKind getStallKind() const { return Kind; }<br>
  unsigned getCyclesLeft() const { return CyclesLeft; }<br>
<br>
diff --git a/llvm/include/llvm/MCA/Stages/InstructionTables.h b/llvm/include/llvm/MCA/Stages/InstructionTables.h<br>
index 35b21b0ba94d2..9617fd49db6e0 100644<br>
--- a/llvm/include/llvm/MCA/Stages/InstructionTables.h<br>
+++ b/llvm/include/llvm/MCA/Stages/InstructionTables.h<br>
@@ -32,7 +32,7 @@ class InstructionTables final : public Stage {<br>
<br>
 public:<br>
  InstructionTables(const MCSchedModel &Model)<br>
-Â Â Â : Stage(), SM(Model), Masks(Model.getNumProcResourceKinds()) {<br>
+Â Â Â : SM(Model), Masks(Model.getNumProcResourceKinds()) {<br>
   computeProcResourceMasks(Model, Masks);<br>
  }<br>
<br>
<br>
diff --git a/llvm/include/llvm/MCA/Stages/RetireStage.h b/llvm/include/llvm/MCA/Stages/RetireStage.h<br>
index b635a01db85e6..aafe2815df150 100644<br>
--- a/llvm/include/llvm/MCA/Stages/RetireStage.h<br>
+++ b/llvm/include/llvm/MCA/Stages/RetireStage.h<br>
@@ -36,7 +36,7 @@ class RetireStage final : public Stage {<br>
<br>
 public:<br>
  RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)<br>
-Â Â Â : Stage(), RCU(R), PRF(F), LSU(LS) {}<br>
+Â Â Â : RCU(R), PRF(F), LSU(LS) {}<br>
<br>
  bool hasWorkToComplete() const override { return !RCU.isEmpty(); }<br>
  Error cycleStart() override;<br>
<br>
diff --git a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h<br>
index d3a5d44ce8ddc..e1f45019b1a92 100644<br>
--- a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h<br>
+++ b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h<br>
@@ -702,7 +702,7 @@ class LineCoverageIterator<br>
<br>
  LineCoverageIterator(const CoverageData &CD, unsigned Line)<br>
    : CD(CD), WrappedSegment(nullptr), Next(CD.begin()), Ended(false),<br>
-Â Â Â Â Line(Line), Segments(), Stats() {<br>
+Â Â Â Â Line(Line) {<br>
   this->operator++();<br>
  }<br>
<br>
<br>
diff --git a/llvm/include/llvm/Remarks/RemarkSerializer.h b/llvm/include/llvm/Remarks/RemarkSerializer.h<br>
index 97fd224ea082d..90e556df87e78 100644<br>
--- a/llvm/include/llvm/Remarks/RemarkSerializer.h<br>
+++ b/llvm/include/llvm/Remarks/RemarkSerializer.h<br>
@@ -48,7 +48,7 @@ struct RemarkSerializer {<br>
<br>
  RemarkSerializer(Format SerializerFormat, raw_ostream &OS,<br>
          SerializerMode Mode)<br>
-Â Â Â : SerializerFormat(SerializerFormat), OS(OS), Mode(Mode), StrTab() {}<br>
+Â Â Â : SerializerFormat(SerializerFormat), OS(OS), Mode(Mode) {}<br>
<br>
  /// This is just an interface.<br>
  virtual ~RemarkSerializer() = default;<br>
<br>
diff --git a/llvm/include/llvm/Support/ScopedPrinter.h b/llvm/include/llvm/Support/ScopedPrinter.h<br>
index 865337e3cc7f5..803ae47793df0 100644<br>
--- a/llvm/include/llvm/Support/ScopedPrinter.h<br>
+++ b/llvm/include/llvm/Support/ScopedPrinter.h<br>
@@ -799,7 +799,7 @@ struct DelimitedScope {<br>
 };<br>
<br>
 struct DictScope : DelimitedScope {<br>
-Â explicit DictScope() : DelimitedScope() {}<br>
+Â explicit DictScope() {}<br>
  explicit DictScope(ScopedPrinter &W) : DelimitedScope(W) { W.objectBegin(); }<br>
<br>
  DictScope(ScopedPrinter &W, StringRef N) : DelimitedScope(W) {<br>
@@ -818,7 +818,7 @@ struct DictScope : DelimitedScope {<br>
 };<br>
<br>
 struct ListScope : DelimitedScope {<br>
-Â explicit ListScope() : DelimitedScope() {}<br>
+Â explicit ListScope() {}<br>
  explicit ListScope(ScopedPrinter &W) : DelimitedScope(W) { W.arrayBegin(); }<br>
<br>
  ListScope(ScopedPrinter &W, StringRef N) : DelimitedScope(W) {<br>
<br>
diff --git a/llvm/include/llvm/Transforms/IPO/Attributor.h b/llvm/include/llvm/Transforms/IPO/Attributor.h<br>
index 1a9dde03aabc6..233f1be04f56b 100644<br>
--- a/llvm/include/llvm/Transforms/IPO/Attributor.h<br>
+++ b/llvm/include/llvm/Transforms/IPO/Attributor.h<br>
@@ -2365,7 +2365,7 @@ struct BooleanState : public IntegerStateBase<bool, 1, 0> {<br>
  using super = IntegerStateBase<bool, 1, 0>;<br>
  using base_t = IntegerStateBase::base_t;<br>
<br>
-Â BooleanState() : super() {}<br>
+Â BooleanState() {}<br>
  BooleanState(base_t Assumed) : super(Assumed) {}<br>
<br>
  /// Set the assumed value to \p Value but never below the known one.<br>
<br>
diff --git a/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h b/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h<br>
index 419729271a236..7ba9d65cae55d 100644<br>
--- a/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h<br>
+++ b/llvm/include/llvm/Transforms/Scalar/LoopPassManager.h<br>
@@ -435,8 +435,7 @@ class FunctionToLoopPassAdaptor<br>
                   bool UseBlockFrequencyInfo = false,<br>
                   bool UseBranchProbabilityInfo = false,<br>
                   bool LoopNestMode = false)<br>
-Â Â Â : Pass(std::move(Pass)), LoopCanonicalizationFPM(),<br>
-Â Â Â Â UseMemorySSA(UseMemorySSA),<br>
+Â Â Â : Pass(std::move(Pass)), UseMemorySSA(UseMemorySSA),<br>
     UseBlockFrequencyInfo(UseBlockFrequencyInfo),<br>
     UseBranchProbabilityInfo(UseBranchProbabilityInfo),<br>
     LoopNestMode(LoopNestMode) {<br>
<br>
diff --git a/llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp b/llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp<br>
index 9467bb3c9b2dd..090dccc53b6ea 100644<br>
--- a/llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp<br>
+++ b/llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp<br>
@@ -63,7 +63,7 @@ using namespace llvm::cflaa;<br>
<br>
 CFLSteensAAResult::CFLSteensAAResult(<br>
   std::function<const TargetLibraryInfo &(Function &F)> GetTLI)<br>
-Â Â : AAResultBase(), GetTLI(std::move(GetTLI)) {}<br>
+Â Â : GetTLI(std::move(GetTLI)) {}<br>
 CFLSteensAAResult::CFLSteensAAResult(CFLSteensAAResult &&Arg)<br>
   : AAResultBase(std::move(Arg)), GetTLI(std::move(Arg.GetTLI)) {}<br>
 CFLSteensAAResult::~CFLSteensAAResult() = default;<br>
<br>
diff --git a/llvm/lib/Analysis/CallGraphSCCPass.cpp b/llvm/lib/Analysis/CallGraphSCCPass.cpp<br>
index f2e5eab72bf28..930cb13c0cb30 100644<br>
--- a/llvm/lib/Analysis/CallGraphSCCPass.cpp<br>
+++ b/llvm/lib/Analysis/CallGraphSCCPass.cpp<br>
@@ -61,7 +61,7 @@ class CGPassManager : public ModulePass, public PMDataManager {<br>
 public:<br>
  static char ID;<br>
<br>
-Â explicit CGPassManager() : ModulePass(ID), PMDataManager() {}<br>
+Â explicit CGPassManager() : ModulePass(ID) {}<br>
<br>
  /// Execute all of the passes scheduled for execution. Keep track of<br>
  /// whether any of the passes modifies the module, and if so, return true.<br>
<br>
diff --git a/llvm/lib/Analysis/DDG.cpp b/llvm/lib/Analysis/DDG.cpp<br>
index da5de75a038cf..7e1357959a3f2 100644<br>
--- a/llvm/lib/Analysis/DDG.cpp<br>
+++ b/llvm/lib/Analysis/DDG.cpp<br>
@@ -106,7 +106,7 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const DDGNode &N) {<br>
 //===--------------------------------------------------------------------===//<br>
<br>
 SimpleDDGNode::SimpleDDGNode(Instruction &I)<br>
-Â : DDGNode(NodeKind::SingleInstruction), InstList() {<br>
+Â Â : DDGNode(NodeKind::SingleInstruction) {<br>
  assert(InstList.empty() && "Expected empty list.");<br>
  InstList.push_back(&I);<br>
 }<br>
<br>
diff --git a/llvm/lib/Analysis/GlobalsModRef.cpp b/llvm/lib/Analysis/GlobalsModRef.cpp<br>
index d00a7c944f10a..53262d88ba51a 100644<br>
--- a/llvm/lib/Analysis/GlobalsModRef.cpp<br>
+++ b/llvm/lib/Analysis/GlobalsModRef.cpp<br>
@@ -102,7 +102,7 @@ class GlobalsAAResult::FunctionInfo {<br>
         "Insufficient low bits to store our flag and ModRef info.");<br>
<br>
 public:<br>
-Â FunctionInfo() : Info() {}<br>
+Â FunctionInfo() {}<br>
  ~FunctionInfo() {<br>
   delete Info.getPointer();<br>
  }<br>
@@ -963,7 +963,7 @@ ModRefInfo GlobalsAAResult::getModRefInfo(const CallBase *Call,<br>
 GlobalsAAResult::GlobalsAAResult(<br>
   const DataLayout &DL,<br>
   std::function<const TargetLibraryInfo &(Function &F)> GetTLI)<br>
-Â Â : AAResultBase(), DL(DL), GetTLI(std::move(GetTLI)) {}<br>
+Â Â : DL(DL), GetTLI(std::move(GetTLI)) {}<br>
<br>
 GlobalsAAResult::GlobalsAAResult(GlobalsAAResult &&Arg)<br>
   : AAResultBase(std::move(Arg)), DL(Arg.DL), GetTLI(std::move(Arg.GetTLI)),<br>
<br>
diff --git a/llvm/lib/Analysis/IVUsers.cpp b/llvm/lib/Analysis/IVUsers.cpp<br>
index d7b202f831890..0f3929f455062 100644<br>
--- a/llvm/lib/Analysis/IVUsers.cpp<br>
+++ b/llvm/lib/Analysis/IVUsers.cpp<br>
@@ -254,7 +254,7 @@ IVStrideUse &IVUsers::AddUser(Instruction *User, Value *Operand) {<br>
<br>
 IVUsers::IVUsers(Loop *L, AssumptionCache *AC, LoopInfo *LI, DominatorTree *DT,<br>
         ScalarEvolution *SE)<br>
-Â Â : L(L), AC(AC), LI(LI), DT(DT), SE(SE), IVUses() {<br>
+Â Â : L(L), AC(AC), LI(LI), DT(DT), SE(SE) {<br>
  // Collect ephemeral values so that AddUsersIfInteresting skips them.<br>
  EphValues.clear();<br>
  CodeMetrics::collectEphemeralValues(L, AC, EphValues);<br>
<br>
diff --git a/llvm/lib/Analysis/LoopCacheAnalysis.cpp b/llvm/lib/Analysis/LoopCacheAnalysis.cpp<br>
index 7b895d8a5dc2a..ba014bd08c987 100644<br>
--- a/llvm/lib/Analysis/LoopCacheAnalysis.cpp<br>
+++ b/llvm/lib/Analysis/LoopCacheAnalysis.cpp<br>
@@ -477,9 +477,8 @@ raw_ostream &llvm::operator<<(raw_ostream &OS, const CacheCost &CC) {<br>
<br>
 CacheCost::CacheCost(const LoopVectorTy &Loops, const LoopInfo &LI,<br>
           ScalarEvolution &SE, TargetTransformInfo &TTI,<br>
-Â Â Â Â Â Â Â Â Â Â Â AAResults &AA, DependenceInfo &DI,<br>
-Â Â Â Â Â Â Â Â Â Â Â Optional<unsigned> TRT)<br>
-Â Â : Loops(Loops), TripCounts(), LoopCosts(),<br>
+Â Â Â Â Â Â Â Â Â Â Â AAResults &AA, DependenceInfo &DI, Optional<unsigned> TRT)<br>
+Â Â : Loops(Loops),<br>
    TRT((TRT == None) ? Optional<unsigned>(TemporalReuseThreshold) : TRT),<br>
    LI(LI), SE(SE), TTI(TTI), AA(AA), DI(DI) {<br>
  assert(!Loops.empty() && "Expecting a non-empty loop vector.");<br>
<br>
diff --git a/llvm/lib/Analysis/LoopPass.cpp b/llvm/lib/Analysis/LoopPass.cpp<br>
index 9e470e998e672..b720bab454e9b 100644<br>
--- a/llvm/lib/Analysis/LoopPass.cpp<br>
+++ b/llvm/lib/Analysis/LoopPass.cpp<br>
@@ -69,8 +69,7 @@ char PrintLoopPassWrapper::ID = 0;<br>
<br>
 char LPPassManager::ID = 0;<br>
<br>
-LPPassManager::LPPassManager()<br>
-Â : FunctionPass(ID), PMDataManager() {<br>
+LPPassManager::LPPassManager() : FunctionPass(ID) {<br>
  LI = nullptr;<br>
  CurrentLoop = nullptr;<br>
 }<br>
<br>
diff --git a/llvm/lib/Analysis/RegionPass.cpp b/llvm/lib/Analysis/RegionPass.cpp<br>
index c20ecff5f9126..10c8569096c6b 100644<br>
--- a/llvm/lib/Analysis/RegionPass.cpp<br>
+++ b/llvm/lib/Analysis/RegionPass.cpp<br>
@@ -30,8 +30,7 @@ using namespace llvm;<br>
<br>
 char RGPassManager::ID = 0;<br>
<br>
-RGPassManager::RGPassManager()<br>
-Â : FunctionPass(ID), PMDataManager() {<br>
+RGPassManager::RGPassManager() : FunctionPass(ID) {<br>
  RI = nullptr;<br>
  CurrentRegion = nullptr;<br>
 }<br>
<br>
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp<br>
index dc5a4d8f85aaa..1d0c106fd5dbd 100644<br>
--- a/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp<br>
+++ b/llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp<br>
@@ -29,7 +29,7 @@<br>
 using namespace llvm;<br>
<br>
 InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)<br>
-Â Â : Renderers(MaxRenderers), MIs() {}<br>
+Â Â : Renderers(MaxRenderers) {}<br>
<br>
 InstructionSelector::InstructionSelector() = default;<br>
<br>
<br>
diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp<br>
index 7e43a0cbbe731..2ee9379cb286b 100644<br>
--- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp<br>
+++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp<br>
@@ -185,7 +185,7 @@ class Polynomial {<br>
  APInt A;<br>
<br>
 public:<br>
-Â Polynomial(Value *V) : ErrorMSBs((unsigned)-1), V(V), B(), A() {<br>
+Â Polynomial(Value *V) : ErrorMSBs((unsigned)-1), V(V) {<br>
   IntegerType *Ty = dyn_cast<IntegerType>(V->getType());<br>
   if (Ty) {<br>
    ErrorMSBs = 0;<br>
@@ -195,12 +195,12 @@ class Polynomial {<br>
  }<br>
<br>
  Polynomial(const APInt &A, unsigned ErrorMSBs = 0)<br>
-Â Â Â : ErrorMSBs(ErrorMSBs), V(nullptr), B(), A(A) {}<br>
+Â Â Â : ErrorMSBs(ErrorMSBs), V(nullptr), A(A) {}<br>
<br>
  Polynomial(unsigned BitWidth, uint64_t A, unsigned ErrorMSBs = 0)<br>
-Â Â Â : ErrorMSBs(ErrorMSBs), V(nullptr), B(), A(BitWidth, A) {}<br>
+Â Â Â : ErrorMSBs(ErrorMSBs), V(nullptr), A(BitWidth, A) {}<br>
<br>
-Â Polynomial() : ErrorMSBs((unsigned)-1), V(nullptr), B(), A() {}<br>
+Â Polynomial() : ErrorMSBs((unsigned)-1), V(nullptr) {}<br>
<br>
  /// Increment and clamp the number of undefined bits.<br>
  void incErrorMSBs(unsigned amt) {<br>
@@ -677,7 +677,7 @@ struct VectorInfo {<br>
  FixedVectorType *const VTy;<br>
<br>
  VectorInfo(FixedVectorType *VTy)<br>
-Â Â Â : BB(nullptr), PV(nullptr), LIs(), Is(), SVI(nullptr), VTy(VTy) {<br>
+Â Â Â : BB(nullptr), PV(nullptr), SVI(nullptr), VTy(VTy) {<br>
   EI = new ElementInfo[VTy->getNumElements()];<br>
  }<br>
<br>
<br>
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp<br>
index d0323eaf3d784..f144639770bca 100644<br>
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp<br>
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp<br>
@@ -182,8 +182,7 @@ static void handleYAMLDiag(const SMDiagnostic &Diag, void *Context) {<br>
 MIRParserImpl::MIRParserImpl(std::unique_ptr<MemoryBuffer> Contents,<br>
               StringRef Filename, LLVMContext &Context,<br>
               std::function<void(Function &)> Callback)<br>
-Â Â : SM(),<br>
-Â Â Â Context(Context),<br>
+Â Â : Context(Context),<br>
    In(SM.getMemoryBuffer(SM.AddNewSourceBuffer(std::move(Contents), SMLoc()))<br>
       ->getBuffer(),<br>
     nullptr, handleYAMLDiag, this),<br>
<br>
diff --git a/llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp b/llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp<br>
index 59fc23983d3d4..5347a7b0d890a 100644<br>
--- a/llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp<br>
+++ b/llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp<br>
@@ -22,8 +22,7 @@<br>
 using namespace llvm;<br>
<br>
 DiagnosticInfoMIROptimization::MachineArgument::MachineArgument(<br>
-Â Â StringRef MKey, const MachineInstr &MI)<br>
-Â Â : Argument() {<br>
+Â Â StringRef MKey, const MachineInstr &MI) {<br>
  Key = std::string(MKey);<br>
<br>
  raw_string_ostream OS(Val);<br>
<br>
diff --git a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp<br>
index 6e05de888cc01..a61a2b2728fa6 100644<br>
--- a/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp<br>
+++ b/llvm/lib/CodeGen/ScoreboardHazardRecognizer.cpp<br>
@@ -30,8 +30,7 @@ using namespace llvm;<br>
 ScoreboardHazardRecognizer::ScoreboardHazardRecognizer(<br>
   const InstrItineraryData *II, const ScheduleDAG *SchedDAG,<br>
   const char *ParentDebugType)<br>
-Â Â : ScheduleHazardRecognizer(), DebugType(ParentDebugType), ItinData(II),<br>
-Â Â Â DAG(SchedDAG) {<br>
+Â Â : DebugType(ParentDebugType), ItinData(II), DAG(SchedDAG) {<br>
  (void)DebugType;<br>
  // Determine the maximum depth of any itinerary. This determines the depth of<br>
  // the scoreboard. We always make the scoreboard at least 1 cycle deep to<br>
<br>
diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp<br>
index d1c2cdeb133b8..697d9df547797 100644<br>
--- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp<br>
+++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp<br>
@@ -108,8 +108,7 @@ static void GetObjCImageInfo(Module &M, unsigned &Version, unsigned &Flags,<br>
 //                 ELF<br>
 //===----------------------------------------------------------------------===//<br>
<br>
-TargetLoweringObjectFileELF::TargetLoweringObjectFileELF()<br>
-Â Â : TargetLoweringObjectFile() {<br>
+TargetLoweringObjectFileELF::TargetLoweringObjectFileELF() {<br>
  SupportDSOLocalEquivalentLowering = true;<br>
 }<br>
<br>
@@ -1139,8 +1138,7 @@ TargetLoweringObjectFileELF::InitializeELF(bool UseInitArray_) {<br>
 //                 MachO<br>
 //===----------------------------------------------------------------------===//<br>
<br>
-TargetLoweringObjectFileMachO::TargetLoweringObjectFileMachO()<br>
-Â : TargetLoweringObjectFile() {<br>
+TargetLoweringObjectFileMachO::TargetLoweringObjectFileMachO() {<br>
  SupportIndirectSymViaGOTPCRel = true;<br>
 }<br>
<br>
@@ -2543,8 +2541,7 @@ MCSection *TargetLoweringObjectFileXCOFF::getSectionForTOCEntry(<br>
 //===----------------------------------------------------------------------===//<br>
 //                 GOFF<br>
 //===----------------------------------------------------------------------===//<br>
-TargetLoweringObjectFileGOFF::TargetLoweringObjectFileGOFF()<br>
-Â Â : TargetLoweringObjectFile() {}<br>
+TargetLoweringObjectFileGOFF::TargetLoweringObjectFileGOFF() {}<br>
<br>
 MCSection *TargetLoweringObjectFileGOFF::getExplicitSectionGlobal(<br>
   const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const {<br>
<br>
diff --git a/llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp b/llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp<br>
index ac217df1ee48c..2524e10cb6c53 100644<br>
--- a/llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp<br>
+++ b/llvm/lib/DebugInfo/PDB/Native/NativeEnumTypes.cpp<br>
@@ -23,7 +23,7 @@ using namespace llvm::pdb;<br>
 NativeEnumTypes::NativeEnumTypes(NativeSession &PDBSession,<br>
                 LazyRandomTypeCollection &Types,<br>
                 std::vector<codeview::TypeLeafKind> Kinds)<br>
-Â Â : Matches(), Index(0), Session(PDBSession) {<br>
+Â Â : Index(0), Session(PDBSession) {<br>
  Optional<TypeIndex> TI = Types.getFirst();<br>
  while (TI) {<br>
   CVType CVT = Types.getType(*TI);<br>
<br>
diff --git a/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp b/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp<br>
index e15bce0d6c4bb..1fb37ce7c57c0 100644<br>
--- a/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp<br>
+++ b/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp<br>
@@ -96,7 +96,7 @@ class GDBJITRegistrationListener : public JITEventListener {<br>
<br>
 public:<br>
  /// Instantiates the JIT service.<br>
-Â GDBJITRegistrationListener() : ObjectBufferMap() {}<br>
+Â GDBJITRegistrationListener() {}<br>
<br>
  /// Unregisters each object that was previously registered and releases all<br>
  /// internal resources.<br>
<br>
diff --git a/llvm/lib/IR/LegacyPassManager.cpp b/llvm/lib/IR/LegacyPassManager.cpp<br>
index bb72bec93066f..4357c95aa9f6d 100644<br>
--- a/llvm/lib/IR/LegacyPassManager.cpp<br>
+++ b/llvm/lib/IR/LegacyPassManager.cpp<br>
@@ -256,9 +256,9 @@ class FunctionPassManagerImpl : public Pass,<br>
  bool wasRun;<br>
 public:<br>
  static char ID;<br>
-Â explicit FunctionPassManagerImpl() :<br>
-Â Â Pass(PT_PassManager, ID), PMDataManager(),<br>
-Â Â PMTopLevelManager(new FPPassManager()), wasRun(false) {}<br>
+Â explicit FunctionPassManagerImpl()<br>
+Â Â Â : Pass(PT_PassManager, ID), PMTopLevelManager(new FPPassManager()),<br>
+Â Â Â Â wasRun(false) {}<br>
<br>
  /// \copydoc FunctionPassManager::add()<br>
  void add(Pass *P) {<br>
@@ -387,8 +387,7 @@ namespace {<br>
 class MPPassManager : public Pass, public PMDataManager {<br>
 public:<br>
  static char ID;<br>
-Â explicit MPPassManager() :<br>
-Â Â Pass(PT_PassManager, ID), PMDataManager() { }<br>
+Â explicit MPPassManager() : Pass(PT_PassManager, ID) {}<br>
<br>
  // Delete on the fly managers.<br>
  ~MPPassManager() override {<br>
@@ -478,9 +477,8 @@ class PassManagerImpl : public Pass,<br>
<br>
 public:<br>
  static char ID;<br>
-Â explicit PassManagerImpl() :<br>
-Â Â Pass(PT_PassManager, ID), PMDataManager(),<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â PMTopLevelManager(new MPPassManager()) {}<br>
+Â explicit PassManagerImpl()<br>
+Â Â Â : Pass(PT_PassManager, ID), PMTopLevelManager(new MPPassManager()) {}<br>
<br>
  /// \copydoc PassManager::add()<br>
  void add(Pass *P) {<br>
<br>
diff --git a/llvm/lib/IR/Module.cpp b/llvm/lib/IR/Module.cpp<br>
index a0485a59d0e08..b3b4b8a80a1c5 100644<br>
--- a/llvm/lib/IR/Module.cpp<br>
+++ b/llvm/lib/IR/Module.cpp<br>
@@ -73,8 +73,7 @@ template class llvm::SymbolTableListTraits<GlobalIFunc>;<br>
<br>
 Module::Module(StringRef MID, LLVMContext &C)<br>
   : Context(C), ValSymTab(std::make_unique<ValueSymbolTable>(-1)),<br>
-Â Â Â Materializer(), ModuleID(std::string(MID)),<br>
-Â Â Â SourceFileName(std::string(MID)), DL("") {<br>
+Â Â Â ModuleID(std::string(MID)), SourceFileName(std::string(MID)), DL("") {<br>
  Context.addModule(this);<br>
 }<br>
<br>
<br>
diff --git a/llvm/lib/InterfaceStub/IFSStub.cpp b/llvm/lib/InterfaceStub/IFSStub.cpp<br>
index 008263f8db9fb..bbc91ada1ded6 100644<br>
--- a/llvm/lib/InterfaceStub/IFSStub.cpp<br>
+++ b/llvm/lib/InterfaceStub/IFSStub.cpp<br>
@@ -29,7 +29,7 @@ IFSStub::IFSStub(IFSStub &&Stub) {<br>
  Symbols = std::move(Stub.Symbols);<br>
 }<br>
<br>
-IFSStubTriple::IFSStubTriple(IFSStubTriple const &Stub) : IFSStub() {<br>
+IFSStubTriple::IFSStubTriple(IFSStubTriple const &Stub) {<br>
  IfsVersion = Stub.IfsVersion;<br>
  Target = Stub.Target;<br>
  SoName = Stub.SoName;<br>
@@ -37,7 +37,7 @@ IFSStubTriple::IFSStubTriple(IFSStubTriple const &Stub) : IFSStub() {<br>
  Symbols = Stub.Symbols;<br>
 }<br>
<br>
-IFSStubTriple::IFSStubTriple(IFSStub const &Stub) : IFSStub() {<br>
+IFSStubTriple::IFSStubTriple(IFSStub const &Stub) {<br>
  IfsVersion = Stub.IfsVersion;<br>
  Target = Stub.Target;<br>
  SoName = Stub.SoName;<br>
<br>
diff --git a/llvm/lib/MC/MCParser/AsmParser.cpp b/llvm/lib/MC/MCParser/AsmParser.cpp<br>
index 705f7159d55b5..5c94174aa161f 100644<br>
--- a/llvm/lib/MC/MCParser/AsmParser.cpp<br>
+++ b/llvm/lib/MC/MCParser/AsmParser.cpp<br>
@@ -159,7 +159,7 @@ class AsmParser : public MCAsmParser {<br>
   int64_t LineNumber;<br>
   SMLoc Loc;<br>
   unsigned Buf;<br>
-Â Â CppHashInfoTy() : Filename(), LineNumber(0), Loc(), Buf(0) {}<br>
+Â Â CppHashInfoTy() : LineNumber(0), Buf(0) {}<br>
  };<br>
  CppHashInfoTy CppHashInfo;<br>
<br>
<br>
diff --git a/llvm/lib/MC/MCParser/MasmParser.cpp b/llvm/lib/MC/MCParser/MasmParser.cpp<br>
index f1704cef46ace..e2dfd339e93e2 100644<br>
--- a/llvm/lib/MC/MCParser/MasmParser.cpp<br>
+++ b/llvm/lib/MC/MCParser/MasmParser.cpp<br>
@@ -424,7 +424,7 @@ class MasmParser : public MCAsmParser {<br>
   int64_t LineNumber;<br>
   SMLoc Loc;<br>
   unsigned Buf;<br>
-Â Â CppHashInfoTy() : Filename(), LineNumber(0), Loc(), Buf(0) {}<br>
+Â Â CppHashInfoTy() : LineNumber(0), Buf(0) {}<br>
  };<br>
  CppHashInfoTy CppHashInfo;<br>
<br>
<br>
diff --git a/llvm/lib/MCA/Stages/DispatchStage.cpp b/llvm/lib/MCA/Stages/DispatchStage.cpp<br>
index 5385142698e67..66228bd5a8629 100644<br>
--- a/llvm/lib/MCA/Stages/DispatchStage.cpp<br>
+++ b/llvm/lib/MCA/Stages/DispatchStage.cpp<br>
@@ -30,7 +30,7 @@ DispatchStage::DispatchStage(const MCSubtargetInfo &Subtarget,<br>
               unsigned MaxDispatchWidth, RetireControlUnit &R,<br>
               RegisterFile &F)<br>
   : DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),<br>
-Â Â Â CarryOver(0U), CarriedOver(), STI(Subtarget), RCU(R), PRF(F) {<br>
+Â Â Â CarryOver(0U), STI(Subtarget), RCU(R), PRF(F) {<br>
  if (!DispatchWidth)<br>
   DispatchWidth = Subtarget.getSchedModel().IssueWidth;<br>
 }<br>
<br>
diff --git a/llvm/lib/MCA/Stages/InOrderIssueStage.cpp b/llvm/lib/MCA/Stages/InOrderIssueStage.cpp<br>
index fa5c0fc66b9ed..abfbc80f17c91 100644<br>
--- a/llvm/lib/MCA/Stages/InOrderIssueStage.cpp<br>
+++ b/llvm/lib/MCA/Stages/InOrderIssueStage.cpp<br>
@@ -47,7 +47,7 @@ InOrderIssueStage::InOrderIssueStage(const MCSubtargetInfo &STI,<br>
                   RegisterFile &PRF, CustomBehaviour &CB,<br>
                   LSUnit &LSU)<br>
   : STI(STI), PRF(PRF), RM(STI.getSchedModel()), CB(CB), LSU(LSU),<br>
-Â Â Â NumIssued(), SI(), CarryOver(), Bandwidth(), LastWriteBackCycle() {}<br>
+Â Â Â NumIssued(), CarryOver(), Bandwidth(), LastWriteBackCycle() {}<br>
<br>
 unsigned InOrderIssueStage::getIssueWidth() const {<br>
  return STI.getSchedModel().IssueWidth;<br>
<br>
diff --git a/llvm/lib/Remarks/BitstreamRemarkSerializer.cpp b/llvm/lib/Remarks/BitstreamRemarkSerializer.cpp<br>
index 36ba935647715..0810bf531db8b 100644<br>
--- a/llvm/lib/Remarks/BitstreamRemarkSerializer.cpp<br>
+++ b/llvm/lib/Remarks/BitstreamRemarkSerializer.cpp<br>
@@ -18,7 +18,7 @@ using namespace llvm::remarks;<br>
<br>
 BitstreamRemarkSerializerHelper::BitstreamRemarkSerializerHelper(<br>
   BitstreamRemarkContainerType ContainerType)<br>
-Â Â : Encoded(), R(), Bitstream(Encoded), ContainerType(ContainerType) {}<br>
+Â Â : Bitstream(Encoded), ContainerType(ContainerType) {}<br>
<br>
 static void push(SmallVectorImpl<uint64_t> &R, StringRef Str) {<br>
  append_range(R, Str);<br>
<br>
diff --git a/llvm/lib/Remarks/RemarkStreamer.cpp b/llvm/lib/Remarks/RemarkStreamer.cpp<br>
index 2f00b8e736700..543b00723659e 100644<br>
--- a/llvm/lib/Remarks/RemarkStreamer.cpp<br>
+++ b/llvm/lib/Remarks/RemarkStreamer.cpp<br>
@@ -26,7 +26,7 @@ static cl::opt<cl::boolOrDefault> EnableRemarksSection(<br>
 RemarkStreamer::RemarkStreamer(<br>
   std::unique_ptr<remarks::RemarkSerializer> RemarkSerializer,<br>
   Optional<StringRef> FilenameIn)<br>
-Â Â : PassFilter(), RemarkSerializer(std::move(RemarkSerializer)),<br>
+Â Â : RemarkSerializer(std::move(RemarkSerializer)),<br>
    Filename(FilenameIn ? Optional<std::string>(FilenameIn->str()) : None) {}<br>
<br>
 Error RemarkStreamer::setFilter(StringRef Filter) {<br>
<br>
diff --git a/llvm/lib/Remarks/RemarkStringTable.cpp b/llvm/lib/Remarks/RemarkStringTable.cpp<br>
index 5f462f01bb9a6..03d93baba0380 100644<br>
--- a/llvm/lib/Remarks/RemarkStringTable.cpp<br>
+++ b/llvm/lib/Remarks/RemarkStringTable.cpp<br>
@@ -20,7 +20,7 @@<br>
 using namespace llvm;<br>
 using namespace llvm::remarks;<br>
<br>
-StringTable::StringTable(const ParsedStringTable &Other) : StrTab() {<br>
+StringTable::StringTable(const ParsedStringTable &Other) {<br>
  for (unsigned i = 0, e = Other.size(); i < e; ++i)<br>
   if (Expected<StringRef> MaybeStr = Other[i])<br>
    add(*MaybeStr);<br>
<br>
diff --git a/llvm/lib/Remarks/YAMLRemarkParser.cpp b/llvm/lib/Remarks/YAMLRemarkParser.cpp<br>
index 3d9996c931aeb..a32629c9f557c 100644<br>
--- a/llvm/lib/Remarks/YAMLRemarkParser.cpp<br>
+++ b/llvm/lib/Remarks/YAMLRemarkParser.cpp<br>
@@ -171,7 +171,7 @@ YAMLRemarkParser::YAMLRemarkParser(StringRef Buf)<br>
<br>
 YAMLRemarkParser::YAMLRemarkParser(StringRef Buf,<br>
                  Optional<ParsedStringTable> StrTab)<br>
-Â Â : RemarkParser{Format::YAML}, StrTab(std::move(StrTab)), LastErrorMessage(),<br>
+Â Â : RemarkParser{Format::YAML}, StrTab(std::move(StrTab)),<br>
    SM(setupSM(LastErrorMessage)), Stream(Buf, SM), YAMLIt(Stream.begin()) {}<br>
<br>
 Error YAMLRemarkParser::error(StringRef Message, yaml::Node &Node) {<br>
<br>
diff --git a/llvm/lib/Support/YAMLParser.cpp b/llvm/lib/Support/YAMLParser.cpp<br>
index 2adf37a511d15..0ba019b3c46a5 100644<br>
--- a/llvm/lib/Support/YAMLParser.cpp<br>
+++ b/llvm/lib/Support/YAMLParser.cpp<br>
@@ -1841,11 +1841,11 @@ bool Scanner::fetchMoreTokens() {<br>
<br>
 Stream::Stream(StringRef Input, SourceMgr &SM, bool ShowColors,<br>
        std::error_code *EC)<br>
-Â Â : scanner(new Scanner(Input, SM, ShowColors, EC)), CurrentDoc() {}<br>
+Â Â : scanner(new Scanner(Input, SM, ShowColors, EC)) {}<br>
<br>
 Stream::Stream(MemoryBufferRef InputBuffer, SourceMgr &SM, bool ShowColors,<br>
        std::error_code *EC)<br>
-Â Â : scanner(new Scanner(InputBuffer, SM, ShowColors, EC)), CurrentDoc() {}<br>
+Â Â : scanner(new Scanner(InputBuffer, SM, ShowColors, EC)) {}<br>
<br>
 Stream::~Stream() = default;<br>
<br>
<br>
diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp<br>
index f7d3dd0bc2225..672739f255991 100644<br>
--- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp<br>
+++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp<br>
@@ -228,7 +228,6 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,<br>
    IsLittle(LittleEndian),<br>
    MinSVEVectorSizeInBits(MinSVEVectorSizeInBitsOverride),<br>
    MaxSVEVectorSizeInBits(MaxSVEVectorSizeInBitsOverride), TargetTriple(TT),<br>
-Â Â Â FrameLowering(),<br>
    InstrInfo(initializeSubtargetDependencies(FS, CPU, TuneCPU)), TSInfo(),<br>
    TLInfo(TM, *this) {<br>
  if (AArch64::isX18ReservedByDefault(TT))<br>
<br>
diff --git a/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp b/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp<br>
index dfc66f0cb4c16..7ed934cfabc0d 100644<br>
--- a/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp<br>
+++ b/llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp<br>
@@ -25,8 +25,7 @@ void AArch64_ELFTargetObjectFile::Initialize(MCContext &Ctx,<br>
  SupportDebugThreadLocalLocation = false;<br>
 }<br>
<br>
-AArch64_MachoTargetObjectFile::AArch64_MachoTargetObjectFile()<br>
-Â : TargetLoweringObjectFileMachO() {<br>
+AArch64_MachoTargetObjectFile::AArch64_MachoTargetObjectFile() {<br>
  SupportGOTPCRelWithOffset = false;<br>
 }<br>
<br>
<br>
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
index 03ef327e93c83..4f8f8078b69d6 100644<br>
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp<br>
@@ -491,7 +491,7 @@ class AArch64Operand : public MCParsedAsmOperand {<br>
 public:<br>
  AArch64Operand(KindTy K, MCContext &Ctx) : Kind(K), Ctx(Ctx) {}<br>
<br>
-Â AArch64Operand(const AArch64Operand &o) : MCParsedAsmOperand(), Ctx(o.Ctx) {<br>
+Â AArch64Operand(const AArch64Operand &o) : Ctx(o.Ctx) {<br>
   Kind = o.Kind;<br>
   StartLoc = o.StartLoc;<br>
   EndLoc = o.EndLoc;<br>
<br>
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
index 3d9a626d3ac38..ea8a7c7b83dac 100644<br>
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp<br>
@@ -472,8 +472,8 @@ class AArch64InstructionSelector : public InstructionSelector {<br>
 AArch64InstructionSelector::AArch64InstructionSelector(<br>
   const AArch64TargetMachine &TM, const AArch64Subtarget &STI,<br>
   const AArch64RegisterBankInfo &RBI)<br>
-Â Â : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),<br>
-Â Â Â TRI(*STI.getRegisterInfo()), RBI(RBI),<br>
+Â Â : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),<br>
+Â Â Â RBI(RBI),<br>
 #define GET_GLOBALISEL_PREDICATES_INIT<br>
 #include "AArch64GenGlobalISel.inc"<br>
 #undef GET_GLOBALISEL_PREDICATES_INIT<br>
<br>
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp<br>
index 515a5c63a5596..92d22881f328c 100644<br>
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp<br>
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp<br>
@@ -42,8 +42,8 @@<br>
<br>
 using namespace llvm;<br>
<br>
-AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)<br>
-Â Â : AArch64GenRegisterBankInfo() {<br>
+AArch64RegisterBankInfo::AArch64RegisterBankInfo(<br>
+Â Â const TargetRegisterInfo &TRI) {<br>
  static llvm::once_flag InitializeRegisterBankFlag;<br>
<br>
  static auto InitializeRegisterBankOnce = [&]() {<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h b/llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h<br>
index 22be014813b03..5ba9b2cd187e7 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h<br>
@@ -26,7 +26,7 @@ class AMDGPUAAResult : public AAResultBase<AMDGPUAAResult> {<br>
  const DataLayout &DL;<br>
<br>
 public:<br>
-Â explicit AMDGPUAAResult(const DataLayout &DL) : AAResultBase(), DL(DL) {}<br>
+Â explicit AMDGPUAAResult(const DataLayout &DL) : DL(DL) {}<br>
  AMDGPUAAResult(AMDGPUAAResult &&Arg)<br>
    : AAResultBase(std::move(Arg)), DL(Arg.DL) {}<br>
<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp<br>
index e16bead81b65e..e5c5d36d1d4fa 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp<br>
@@ -46,8 +46,7 @@ static cl::opt<bool> AllowRiskySelect(<br>
 AMDGPUInstructionSelector::AMDGPUInstructionSelector(<br>
   const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI,<br>
   const AMDGPUTargetMachine &TM)<br>
-Â Â : InstructionSelector(), TII(*STI.getInstrInfo()),<br>
-Â Â Â TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),<br>
+Â Â : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM),<br>
    STI(STI),<br>
    EnableLateStructurizeCFG(AMDGPUTargetMachine::EnableLateStructurizeCFG),<br>
 #define GET_GLOBALISEL_PREDICATES_INIT<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h<br>
index c97223b047e88..fb6a64b75c20f 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h<br>
@@ -356,7 +356,7 @@ class AMDGPULibFuncImpl : public AMDGPULibFuncBase {<br>
 /// Wrapper class for AMDGPULIbFuncImpl<br>
 class AMDGPULibFunc : public AMDGPULibFuncBase {<br>
 public:<br>
-Â explicit AMDGPULibFunc() : Impl(std::unique_ptr<AMDGPULibFuncImpl>()) {}<br>
+Â explicit AMDGPULibFunc() {}<br>
  AMDGPULibFunc(const AMDGPULibFunc &F);<br>
  /// Clone a mangled library func with the Id \p Id and argument info from \p<br>
  /// CopyFrom.<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp<br>
index c60012bcfe2e8..ab463ce8940dc 100644<br>
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp<br>
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp<br>
@@ -193,9 +193,7 @@ class ApplyRegBankMapping final : public GISelChangeObserver {<br>
<br>
 }<br>
 AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const GCNSubtarget &ST)<br>
-Â Â : AMDGPUGenRegisterBankInfo(),<br>
-Â Â Â Subtarget(ST),<br>
-Â Â Â TRI(Subtarget.getRegisterInfo()),<br>
+Â Â : Subtarget(ST), TRI(Subtarget.getRegisterInfo()),<br>
    TII(Subtarget.getInstrInfo()) {<br>
<br>
  // HACK: Until this is fully tablegen'd.<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
index 2bb59086f391b..c71205b17a1a5 100644<br>
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp<br>
@@ -62,7 +62,7 @@ class AMDGPUOperand : public MCParsedAsmOperand {<br>
<br>
 public:<br>
  AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)<br>
-Â Â : MCParsedAsmOperand(), Kind(Kind_), AsmParser(AsmParser_) {}<br>
+Â Â Â : Kind(Kind_), AsmParser(AsmParser_) {}<br>
<br>
  using Ptr = std::unique_ptr<AMDGPUOperand>;<br>
<br>
<br>
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp<br>
index 7708579a4491d..ded3fb7ab8d9f 100644<br>
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp<br>
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp<br>
@@ -15,8 +15,7 @@<br>
 using namespace llvm;<br>
<br>
 AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,<br>
-Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const MCTargetOptions &Options)<br>
-Â Â : MCAsmInfoELF() {<br>
+Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const MCTargetOptions &Options) {<br>
  CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4;<br>
  StackGrowsUp = true;<br>
  HasSingleParameterDotFile = false;<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp<br>
index f083fa6662e93..0d201a67af461 100644<br>
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.cpp<br>
@@ -164,7 +164,7 @@ static bool getBaseOffset(const MachineInstr &MI, const MachineOperand *&BaseOp,<br>
<br>
 ARMBankConflictHazardRecognizer::ARMBankConflictHazardRecognizer(<br>
   const ScheduleDAG *DAG, int64_t CPUBankMask, bool CPUAssumeITCMConflict)<br>
-Â Â : ScheduleHazardRecognizer(), MF(DAG->MF), DL(DAG->MF.getDataLayout()),<br>
+Â Â : MF(DAG->MF), DL(DAG->MF.getDataLayout()),<br>
    DataMask(DataBankMask.getNumOccurrences() ? int64_t(DataBankMask)<br>
                         : CPUBankMask),<br>
    AssumeITCMBankConflict(AssumeITCMConflict.getNumOccurrences()<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMHazardRecognizer.h b/llvm/lib/Target/ARM/ARMHazardRecognizer.h<br>
index c1f1bcd0a629b..66a1477e5e082 100644<br>
--- a/llvm/lib/Target/ARM/ARMHazardRecognizer.h<br>
+++ b/llvm/lib/Target/ARM/ARMHazardRecognizer.h<br>
@@ -34,7 +34,7 @@ class ARMHazardRecognizerFPMLx : public ScheduleHazardRecognizer {<br>
  unsigned FpMLxStalls = 0;<br>
<br>
 public:<br>
-Â ARMHazardRecognizerFPMLx() : ScheduleHazardRecognizer() { MaxLookAhead = 1; }<br>
+Â ARMHazardRecognizerFPMLx() { MaxLookAhead = 1; }<br>
<br>
  HazardType getHazardType(SUnit *SU, int Stalls) override;<br>
  void Reset() override;<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp<br>
index 5dee5e04af815..00db13f2eb520 100644<br>
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp<br>
@@ -28,8 +28,7 @@<br>
 #include "llvm/MC/MCInst.h"<br>
 using namespace llvm;<br>
<br>
-ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)<br>
-Â Â : ARMBaseInstrInfo(STI), RI() {}<br>
+ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {}<br>
<br>
 /// Return the noop instruction to use for a noop.<br>
 MCInst ARMInstrInfo::getNop() const {<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp<br>
index 8be4e3f160e30..188b5562cac93 100644<br>
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp<br>
@@ -171,8 +171,8 @@ createARMInstructionSelector(const ARMBaseTargetMachine &TM,<br>
 ARMInstructionSelector::ARMInstructionSelector(const ARMBaseTargetMachine &TM,<br>
                        const ARMSubtarget &STI,<br>
                        const ARMRegisterBankInfo &RBI)<br>
-Â Â : InstructionSelector(), TII(*STI.getInstrInfo()),<br>
-Â Â Â TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI),<br>
+Â Â : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI),<br>
+Â Â Â STI(STI), Opcodes(STI),<br>
 #define GET_GLOBALISEL_PREDICATES_INIT<br>
 #include "ARMGenGlobalISel.inc"<br>
 #undef GET_GLOBALISEL_PREDICATES_INIT<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp<br>
index 1a7f10a13ed30..2523752a717e4 100644<br>
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp<br>
@@ -129,8 +129,7 @@ static void checkValueMappings() {<br>
 } // end namespace arm<br>
 } // end namespace llvm<br>
<br>
-ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)<br>
-Â Â : ARMGenRegisterBankInfo() {<br>
+ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) {<br>
  // We have only one set of register banks, whatever the subtarget<br>
  // is. Therefore, the initialization of the RegBanks table should be<br>
  // done only once. Indeed the table of all register banks<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp<br>
index 6649750bb3883..ff4647dd46fd9 100644<br>
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp<br>
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp<br>
@@ -15,4 +15,4 @@ using namespace llvm;<br>
<br>
 void ARMRegisterInfo::anchor() { }<br>
<br>
-ARMRegisterInfo::ARMRegisterInfo() : ARMBaseRegisterInfo() {}<br>
+ARMRegisterInfo::ARMRegisterInfo() {}<br>
<br>
diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.h b/llvm/lib/Target/ARM/ARMTargetObjectFile.h<br>
index f86774beb397f..47334b9a8a453 100644<br>
--- a/llvm/lib/Target/ARM/ARMTargetObjectFile.h<br>
+++ b/llvm/lib/Target/ARM/ARMTargetObjectFile.h<br>
@@ -17,8 +17,7 @@ namespace llvm {<br>
<br>
 class ARMElfTargetObjectFile : public TargetLoweringObjectFileELF {<br>
 public:<br>
-Â ARMElfTargetObjectFile()<br>
-Â Â Â : TargetLoweringObjectFileELF() {<br>
+Â ARMElfTargetObjectFile() {<br>
   PLTRelativeVariantKind = MCSymbolRefExpr::VK_ARM_PREL31;<br>
  }<br>
<br>
<br>
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
index c8cec88d6e11d..c7734cc2cf11d 100644<br>
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
@@ -921,7 +921,7 @@ class ARMOperand : public MCParsedAsmOperand {<br>
  };<br>
<br>
 public:<br>
-Â ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>
+Â ARMOperand(KindTy K) : Kind(K) {}<br>
<br>
  /// getStartLoc - Get the location of the first token of this operand.<br>
  SMLoc getStartLoc() const override { return StartLoc; }<br>
<br>
diff --git a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp<br>
index 4b18f5e20d406..1a36c2ca9152e 100644<br>
--- a/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp<br>
+++ b/llvm/lib/Target/ARM/Thumb1InstrInfo.cpp<br>
@@ -21,7 +21,7 @@<br>
 using namespace llvm;<br>
<br>
 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)<br>
-Â Â : ARMBaseInstrInfo(STI), RI() {}<br>
+Â Â : ARMBaseInstrInfo(STI) {}<br>
<br>
 /// Return the noop instruction to use for a noop.<br>
 MCInst Thumb1InstrInfo::getNop() const {<br>
<br>
diff --git a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp<br>
index 4da6f6ab6994f..5d2bc4ebe1917 100644<br>
--- a/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp<br>
+++ b/llvm/lib/Target/ARM/ThumbRegisterInfo.cpp<br>
@@ -37,7 +37,7 @@ extern cl::opt<bool> ReuseFrameIndexVals;<br>
<br>
 using namespace llvm;<br>
<br>
-ThumbRegisterInfo::ThumbRegisterInfo() : ARMBaseRegisterInfo() {}<br>
+ThumbRegisterInfo::ThumbRegisterInfo() {}<br>
<br>
 const TargetRegisterClass *<br>
 ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,<br>
<br>
diff --git a/llvm/lib/Target/AVR/AVRSubtarget.cpp b/llvm/lib/Target/AVR/AVRSubtarget.cpp<br>
index 990e1c57e63f3..820efe79bf8af 100644<br>
--- a/llvm/lib/Target/AVR/AVRSubtarget.cpp<br>
+++ b/llvm/lib/Target/AVR/AVRSubtarget.cpp<br>
@@ -39,8 +39,6 @@ AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU,<br>
    m_supportsRMW(false), m_supportsMultiplication(false), m_hasBREAK(false),<br>
    m_hasTinyEncoding(false), m_hasMemMappedGPR(false),<br>
    m_FeatureSetDummy(false),<br>
-<br>
-Â Â Â InstrInfo(), FrameLowering(),<br>
    TLInfo(TM, initializeSubtargetDependencies(CPU, FS, TM)), TSInfo() {<br>
  // Parse features string.<br>
  ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);<br>
<br>
diff --git a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp<br>
index 95c737aa272ef..f19e7840eb310 100644<br>
--- a/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp<br>
+++ b/llvm/lib/Target/AVR/AsmParser/AVRAsmParser.cpp<br>
@@ -107,13 +107,13 @@ class AVROperand : public MCParsedAsmOperand {<br>
<br>
 public:<br>
  AVROperand(StringRef Tok, SMLoc const &S)<br>
-Â Â Â : Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}<br>
+Â Â Â : Kind(k_Token), Tok(Tok), Start(S), End(S) {}<br>
  AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)<br>
-Â Â Â : Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}<br>
+Â Â Â : Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}<br>
  AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)<br>
-Â Â Â : Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}<br>
+Â Â Â : Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}<br>
  AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)<br>
-Â Â Â : Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}<br>
+Â Â Â : Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}<br>
<br>
  struct RegisterImmediate {<br>
   unsigned Reg;<br>
<br>
diff --git a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp<br>
index 50298bf5e943e..d55510a2455c6 100644<br>
--- a/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp<br>
+++ b/llvm/lib/Target/BPF/AsmParser/BPFAsmParser.cpp<br>
@@ -101,10 +101,10 @@ struct BPFOperand : public MCParsedAsmOperand {<br>
   ImmOp Imm;<br>
  };<br>
<br>
-Â BPFOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>
+Â BPFOperand(KindTy K) : Kind(K) {}<br>
<br>
 public:<br>
-Â BPFOperand(const BPFOperand &o) : MCParsedAsmOperand() {<br>
+Â BPFOperand(const BPFOperand &o) {<br>
   Kind = o.Kind;<br>
   StartLoc = o.StartLoc;<br>
   EndLoc = o.EndLoc;<br>
<br>
diff --git a/llvm/lib/Target/BPF/BPFSubtarget.cpp b/llvm/lib/Target/BPF/BPFSubtarget.cpp<br>
index 77e3cd393f875..e4d98b85e58b8 100644<br>
--- a/llvm/lib/Target/BPF/BPFSubtarget.cpp<br>
+++ b/llvm/lib/Target/BPF/BPFSubtarget.cpp<br>
@@ -59,6 +59,6 @@ void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {<br>
<br>
 BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,<br>
              const std::string &FS, const TargetMachine &TM)<br>
-Â Â : BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),<br>
+Â Â : BPFGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),<br>
    FrameLowering(initializeSubtargetDependencies(CPU, FS)),<br>
    TLInfo(TM, *this) {}<br>
<br>
diff --git a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
index d131cf896834d..58f5ea78c5416 100644<br>
--- a/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
+++ b/llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp<br>
@@ -211,12 +211,10 @@ struct HexagonOperand : public MCParsedAsmOperand {<br>
   struct ImmTy Imm;<br>
  };<br>
<br>
-Â HexagonOperand(KindTy K, MCContext &Context)<br>
-Â Â Â : MCParsedAsmOperand(), Kind(K), Context(Context) {}<br>
+Â HexagonOperand(KindTy K, MCContext &Context) : Kind(K), Context(Context) {}<br>
<br>
 public:<br>
-Â HexagonOperand(const HexagonOperand &o)<br>
-Â Â Â : MCParsedAsmOperand(), Context(o.Context) {<br>
+Â HexagonOperand(const HexagonOperand &o) : Context(o.Context) {<br>
   Kind = o.Kind;<br>
   StartLoc = o.StartLoc;<br>
   EndLoc = o.EndLoc;<br>
<br>
diff --git a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
index 2679e399852f2..091542f2e76a3 100644<br>
--- a/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
+++ b/llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
@@ -1652,7 +1652,7 @@ struct WeightedLeaf {<br>
  int Weight;<br>
  int InsertionOrder;<br>
<br>
-Â WeightedLeaf() : Value(SDValue()) { }<br>
+Â WeightedLeaf() {}<br>
<br>
  WeightedLeaf(SDValue Value, int Weight, int InsertionOrder) :<br>
   Value(Value), Weight(Weight), InsertionOrder(InsertionOrder) {<br>
<br>
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp<br>
index 5f094dfeb95c9..a47d414af831f 100644<br>
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp<br>
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp<br>
@@ -204,7 +204,7 @@ HexagonMCChecker::HexagonMCChecker(MCContext &Context, MCInstrInfo const &MCII,<br>
                  MCSubtargetInfo const &STI, MCInst &mcb,<br>
                  MCRegisterInfo const &ri, bool ReportErrors)<br>
   : Context(Context), MCB(mcb), RI(ri), MCII(MCII), STI(STI),<br>
-Â Â Â ReportErrors(ReportErrors), ReversePairs() {<br>
+Â Â Â ReportErrors(ReportErrors) {<br>
  init();<br>
 }<br>
<br>
@@ -212,8 +212,7 @@ HexagonMCChecker::HexagonMCChecker(HexagonMCChecker const &Other,<br>
                  MCSubtargetInfo const &STI,<br>
                  bool CopyReportErrors)<br>
   : Context(Other.Context), MCB(Other.MCB), RI(Other.RI), MCII(Other.MCII),<br>
-Â Â Â STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false),<br>
-Â Â Â ReversePairs() {<br>
+Â Â Â STI(STI), ReportErrors(CopyReportErrors ? Other.ReportErrors : false) {<br>
  init();<br>
 }<br>
<br>
<br>
diff --git a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp<br>
index a994bd7e57a40..660215ca74353 100644<br>
--- a/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp<br>
+++ b/llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp<br>
@@ -141,7 +141,7 @@ struct LanaiOperand : public MCParsedAsmOperand {<br>
   struct MemOp Mem;<br>
  };<br>
<br>
-Â explicit LanaiOperand(KindTy Kind) : MCParsedAsmOperand(), Kind(Kind) {}<br>
+Â explicit LanaiOperand(KindTy Kind) : Kind(Kind) {}<br>
<br>
 public:<br>
  // The functions below are used by the autogenerated ASM matcher and hence to<br>
<br>
diff --git a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp<br>
index d9d7847a0c5ab..37a4843e1bc40 100644<br>
--- a/llvm/lib/Target/Lanai/LanaiSubtarget.cpp<br>
+++ b/llvm/lib/Target/Lanai/LanaiSubtarget.cpp<br>
@@ -43,4 +43,4 @@ LanaiSubtarget::LanaiSubtarget(const Triple &TargetTriple, StringRef Cpu,<br>
                CodeGenOpt::Level /*OptLevel*/)<br>
   : LanaiGenSubtargetInfo(TargetTriple, Cpu, /*TuneCPU*/ Cpu, FeatureString),<br>
    FrameLowering(initializeSubtargetDependencies(Cpu, FeatureString)),<br>
-Â Â Â InstrInfo(), TLInfo(TM, *this), TSInfo() {}<br>
+Â Â Â TLInfo(TM, *this) {}<br>
<br>
diff --git a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp<br>
index c1677baf52a7a..13cba8b079a9b 100644<br>
--- a/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp<br>
+++ b/llvm/lib/Target/MSP430/AsmParser/MSP430AsmParser.cpp<br>
@@ -114,13 +114,14 @@ class MSP430Operand : public MCParsedAsmOperand {<br>
<br>
 public:<br>
  MSP430Operand(StringRef Tok, SMLoc const &S)<br>
-Â Â Â : Base(), Kind(k_Tok), Tok(Tok), Start(S), End(S) {}<br>
+Â Â Â : Kind(k_Tok), Tok(Tok), Start(S), End(S) {}<br>
  MSP430Operand(KindTy Kind, unsigned Reg, SMLoc const &S, SMLoc const &E)<br>
-Â Â Â : Base(), Kind(Kind), Reg(Reg), Start(S), End(E) {}<br>
+Â Â Â : Kind(Kind), Reg(Reg), Start(S), End(E) {}<br>
  MSP430Operand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)<br>
-Â Â Â : Base(), Kind(k_Imm), Imm(Imm), Start(S), End(E) {}<br>
-Â MSP430Operand(unsigned Reg, MCExpr const *Expr, SMLoc const &S, SMLoc const &E)<br>
-Â Â Â : Base(), Kind(k_Mem), Mem({Reg, Expr}), Start(S), End(E) {}<br>
+Â Â Â : Kind(k_Imm), Imm(Imm), Start(S), End(E) {}<br>
+Â MSP430Operand(unsigned Reg, MCExpr const *Expr, SMLoc const &S,<br>
+Â Â Â Â Â Â Â Â SMLoc const &E)<br>
+Â Â Â : Kind(k_Mem), Mem({Reg, Expr}), Start(S), End(E) {}<br>
<br>
  void addRegOperands(MCInst &Inst, unsigned N) const {<br>
   assert((Kind == k_Reg || Kind == k_IndReg || Kind == k_PostIndReg) &&<br>
<br>
diff --git a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp<br>
index 2fd58717c4dbe..0604d47597e25 100644<br>
--- a/llvm/lib/Target/MSP430/MSP430Subtarget.cpp<br>
+++ b/llvm/lib/Target/MSP430/MSP430Subtarget.cpp<br>
@@ -57,5 +57,5 @@ MSP430Subtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {<br>
<br>
 MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU,<br>
                 const std::string &FS, const TargetMachine &TM)<br>
-Â Â : MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), FrameLowering(),<br>
+Â Â : MSP430GenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),<br>
    InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {}<br>
<br>
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp<br>
index 01b5dff2e4486..736c41f8ac035 100644<br>
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp<br>
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp<br>
@@ -827,8 +827,7 @@ class MipsOperand : public MCParsedAsmOperand {<br>
  } Kind;<br>
<br>
 public:<br>
-Â MipsOperand(KindTy K, MipsAsmParser &Parser)<br>
-Â Â Â : MCParsedAsmOperand(), Kind(K), AsmParser(Parser) {}<br>
+Â MipsOperand(KindTy K, MipsAsmParser &Parser) : Kind(K), AsmParser(Parser) {}<br>
<br>
  ~MipsOperand() override {<br>
   switch (Kind) {<br>
<br>
diff --git a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp<br>
index f6f43da9abf84..563118dfe627d 100644<br>
--- a/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp<br>
+++ b/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp<br>
@@ -37,7 +37,7 @@ using namespace llvm;<br>
<br>
 #define DEBUG_TYPE "mips16-registerinfo"<br>
<br>
-Mips16RegisterInfo::Mips16RegisterInfo() : MipsRegisterInfo() {}<br>
+Mips16RegisterInfo::Mips16RegisterInfo() {}<br>
<br>
 bool Mips16RegisterInfo::requiresRegisterScavenging<br>
  (const MachineFunction &MF) const {<br>
<br>
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp<br>
index 6d44ce2ab5635..59f158688b163 100644<br>
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp<br>
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp<br>
@@ -80,8 +80,8 @@ class MipsInstructionSelector : public InstructionSelector {<br>
 MipsInstructionSelector::MipsInstructionSelector(<br>
   const MipsTargetMachine &TM, const MipsSubtarget &STI,<br>
   const MipsRegisterBankInfo &RBI)<br>
-Â Â : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),<br>
-Â Â Â TRI(*STI.getRegisterInfo()), RBI(RBI),<br>
+Â Â : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),<br>
+Â Â Â RBI(RBI),<br>
<br>
 #define GET_GLOBALISEL_PREDICATES_INIT<br>
 #include "MipsGenGlobalISel.inc"<br>
<br>
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp<br>
index 04b69c66bc0d1..2cb59e6960313 100644<br>
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp<br>
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp<br>
@@ -73,8 +73,7 @@ RegisterBankInfo::ValueMapping ValueMappings[] = {<br>
<br>
 using namespace llvm;<br>
<br>
-MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)<br>
-Â Â : MipsGenRegisterBankInfo() {}<br>
+MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI) {}<br>
<br>
 const RegisterBank &<br>
 MipsRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,<br>
<br>
diff --git a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp<br>
index b05e9ad827c40..d6481793ef495 100644<br>
--- a/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp<br>
+++ b/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp<br>
@@ -38,7 +38,7 @@ using namespace llvm;<br>
<br>
 #define DEBUG_TYPE "mips-reg-info"<br>
<br>
-MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}<br>
+MipsSERegisterInfo::MipsSERegisterInfo() {}<br>
<br>
 bool MipsSERegisterInfo::<br>
 requiresRegisterScavenging(const MachineFunction &MF) const {<br>
<br>
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp<br>
index 953d95e55f658..8df6f13aa68e1 100644<br>
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp<br>
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp<br>
@@ -27,7 +27,7 @@ using namespace llvm;<br>
 // Pin the vtable to this file.<br>
 void NVPTXInstrInfo::anchor() {}<br>
<br>
-NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}<br>
+NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {}<br>
<br>
 void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,<br>
                 MachineBasicBlock::iterator I,<br>
<br>
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp<br>
index 05c20369abf45..5a6440c91fcad 100644<br>
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp<br>
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp<br>
@@ -49,8 +49,8 @@ NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,<br>
                const std::string &FS,<br>
                const NVPTXTargetMachine &TM)<br>
   : NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),<br>
-Â Â Â SmVersion(20), TM(TM), InstrInfo(),<br>
-Â Â Â TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), FrameLowering() {}<br>
+Â Â Â SmVersion(20), TM(TM),<br>
+Â Â Â TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {}<br>
<br>
 bool NVPTXSubtarget::hasImageHandles() const {<br>
  // Enable handles for Kepler+, where CUDA supports indirect surfaces and<br>
<br>
diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h b/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h<br>
index 366d92a5a8054..4645671a0cd86 100644<br>
--- a/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h<br>
+++ b/llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h<br>
@@ -17,7 +17,7 @@ namespace llvm {<br>
<br>
 class NVPTXTargetObjectFile : public TargetLoweringObjectFile {<br>
 public:<br>
-Â NVPTXTargetObjectFile() : TargetLoweringObjectFile() {}<br>
+Â NVPTXTargetObjectFile() {}<br>
<br>
  ~NVPTXTargetObjectFile() override;<br>
<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp<br>
index ded922329ebf6..1f509afb723b4 100644<br>
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp<br>
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp<br>
@@ -201,9 +201,10 @@ struct PPCOperand : public MCParsedAsmOperand {<br>
   struct TLSRegOp TLSReg;<br>
  };<br>
<br>
-Â PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>
+Â PPCOperand(KindTy K) : Kind(K) {}<br>
+<br>
 public:<br>
-Â PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {<br>
+Â PPCOperand(const PPCOperand &o) {<br>
   Kind = o.Kind;<br>
   StartLoc = o.StartLoc;<br>
   EndLoc = o.EndLoc;<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp<br>
index 7d64816ed6c7f..0cd8350e3fdda 100644<br>
--- a/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp<br>
+++ b/llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp<br>
@@ -65,8 +65,7 @@ class PPCInstructionSelector : public InstructionSelector {<br>
 PPCInstructionSelector::PPCInstructionSelector(const PPCTargetMachine &TM,<br>
                        const PPCSubtarget &STI,<br>
                        const PPCRegisterBankInfo &RBI)<br>
-Â Â : InstructionSelector(), TII(*STI.getInstrInfo()),<br>
-Â Â Â TRI(*STI.getRegisterInfo()), RBI(RBI),<br>
+Â Â : TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),<br>
 #define GET_GLOBALISEL_PREDICATES_INIT<br>
 #include "PPCGenGlobalISel.inc"<br>
 #undef GET_GLOBALISEL_PREDICATES_INIT<br>
<br>
diff --git a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp<br>
index 6af79324919cc..58165fcaac03f 100644<br>
--- a/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp<br>
+++ b/llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp<br>
@@ -23,5 +23,4 @@<br>
<br>
 using namespace llvm;<br>
<br>
-PPCRegisterBankInfo::PPCRegisterBankInfo(const TargetRegisterInfo &TRI)<br>
-Â Â : PPCGenRegisterBankInfo() {}<br>
+PPCRegisterBankInfo::PPCRegisterBankInfo(const TargetRegisterInfo &TRI) {}<br>
<br>
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp<br>
index 75592dd4c6f54..858e78076b566 100644<br>
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp<br>
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp<br>
@@ -302,10 +302,10 @@ struct RISCVOperand : public MCParsedAsmOperand {<br>
   struct VTypeOp VType;<br>
  };<br>
<br>
-Â RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>
+Â RISCVOperand(KindTy K) : Kind(K) {}<br>
<br>
 public:<br>
-Â RISCVOperand(const RISCVOperand &o) : MCParsedAsmOperand() {<br>
+Â RISCVOperand(const RISCVOperand &o) {<br>
   Kind = o.Kind;<br>
   IsRV64 = o.IsRV64;<br>
   StartLoc = o.StartLoc;<br>
<br>
diff --git a/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp<br>
index 4d1f47da209d0..8dfd71ac0b6bd 100644<br>
--- a/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp<br>
+++ b/llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp<br>
@@ -69,8 +69,7 @@ class RISCVInstructionSelector : public InstructionSelector {<br>
 RISCVInstructionSelector::RISCVInstructionSelector(<br>
   const RISCVTargetMachine &TM, const RISCVSubtarget &STI,<br>
   const RISCVRegisterBankInfo &RBI)<br>
-Â Â : InstructionSelector(), STI(STI), TII(*STI.getInstrInfo()),<br>
-Â Â Â TRI(*STI.getRegisterInfo()), RBI(RBI),<br>
+Â Â : STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()), RBI(RBI),<br>
<br>
 #define GET_GLOBALISEL_PREDICATES_INIT<br>
 #include "RISCVGenGlobalISel.inc"<br>
<br>
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp<br>
index bd3b95a98b9f7..4ff3a44f35118 100644<br>
--- a/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp<br>
+++ b/llvm/lib/Target/RISCV/RISCVRegisterBankInfo.cpp<br>
@@ -22,5 +22,4 @@<br>
<br>
 using namespace llvm;<br>
<br>
-RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI)<br>
-Â Â : RISCVGenRegisterBankInfo() {}<br>
+RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI) {}<br>
<br>
diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp<br>
index 48e6903bd1b12..af3304f0907d0 100644<br>
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp<br>
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp<br>
@@ -257,7 +257,7 @@ class SparcOperand : public MCParsedAsmOperand {<br>
  };<br>
<br>
 public:<br>
-Â SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>
+Â SparcOperand(KindTy K) : Kind(K) {}<br>
<br>
  bool isToken() const override { return Kind == k_Token; }<br>
  bool isReg() const override { return Kind == k_Register; }<br>
<br>
diff --git a/llvm/lib/Target/Sparc/SparcTargetObjectFile.h b/llvm/lib/Target/Sparc/SparcTargetObjectFile.h<br>
index 9bbe602b32b30..f30ddc7b4955d 100644<br>
--- a/llvm/lib/Target/Sparc/SparcTargetObjectFile.h<br>
+++ b/llvm/lib/Target/Sparc/SparcTargetObjectFile.h<br>
@@ -18,9 +18,7 @@ class TargetMachine;<br>
<br>
 class SparcELFTargetObjectFile : public TargetLoweringObjectFileELF {<br>
 public:<br>
-Â SparcELFTargetObjectFile() :<br>
-Â Â TargetLoweringObjectFileELF()<br>
-Â {}<br>
+Â SparcELFTargetObjectFile() {}<br>
<br>
  void Initialize(MCContext &Ctx, const TargetMachine &TM) override;<br>
<br>
<br>
diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp<br>
index 39a82e2c07e02..cf55318d328df 100644<br>
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp<br>
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp<br>
@@ -62,8 +62,7 @@ struct SystemZAddressingMode {<br>
  bool IncludesDynAlloc;<br>
<br>
  SystemZAddressingMode(AddrForm form, DispRange dr)<br>
-Â Â : Form(form), DR(dr), Base(), Disp(0), Index(),<br>
-Â Â Â IncludesDynAlloc(false) {}<br>
+Â Â Â : Form(form), DR(dr), Disp(0), IncludesDynAlloc(false) {}<br>
<br>
  // True if the address can have an index register.<br>
  bool hasIndexField() { return Form != FormBD; }<br>
<br>
diff --git a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp<br>
index 0f03d96655bff..75c0d454d9047 100644<br>
--- a/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp<br>
+++ b/llvm/lib/Target/SystemZ/SystemZSubtarget.cpp<br>
@@ -89,7 +89,7 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,<br>
    HasSoftFloat(false), TargetTriple(TT),<br>
    SpecialRegisters(initializeSpecialRegisters()),<br>
    InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),<br>
-Â Â Â TSInfo(), FrameLowering(SystemZFrameLowering::create(*this)) {}<br>
+Â Â Â FrameLowering(SystemZFrameLowering::create(*this)) {}<br>
<br>
 bool SystemZSubtarget::enableSubRegLiveness() const {<br>
  return UseSubRegLiveness;<br>
<br>
diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp<br>
index fd9dc32b04f54..4a318e493c522 100644<br>
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp<br>
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp<br>
@@ -210,7 +210,7 @@ class VEOperand : public MCParsedAsmOperand {<br>
  };<br>
<br>
 public:<br>
-Â VEOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>
+Â VEOperand(KindTy K) : Kind(K) {}<br>
<br>
  bool isToken() const override { return Kind == k_Token; }<br>
  bool isReg() const override { return Kind == k_Register; }<br>
<br>
diff --git a/llvm/lib/Target/VE/VEMachineFunctionInfo.h b/llvm/lib/Target/VE/VEMachineFunctionInfo.h<br>
index 16b25fed3f11d..3160f6a552d78 100644<br>
--- a/llvm/lib/Target/VE/VEMachineFunctionInfo.h<br>
+++ b/llvm/lib/Target/VE/VEMachineFunctionInfo.h<br>
@@ -29,10 +29,9 @@ class VEMachineFunctionInfo : public MachineFunctionInfo {<br>
  bool IsLeafProc;<br>
<br>
 public:<br>
-Â VEMachineFunctionInfo()<br>
-Â Â Â : GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {}<br>
+Â VEMachineFunctionInfo() : VarArgsFrameOffset(0), IsLeafProc(false) {}<br>
  explicit VEMachineFunctionInfo(MachineFunction &MF)<br>
-Â Â Â : GlobalBaseReg(), VarArgsFrameOffset(0), IsLeafProc(false) {}<br>
+Â Â Â : VarArgsFrameOffset(0), IsLeafProc(false) {}<br>
<br>
  Register getGlobalBaseReg() const { return GlobalBaseReg; }<br>
  void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; }<br>
<br>
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp<br>
index add3c799f4aa3..103b634ecf5bc 100644<br>
--- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp<br>
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp<br>
@@ -42,9 +42,8 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,<br>
                      const std::string &FS,<br>
                      const TargetMachine &TM)<br>
   : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),<br>
-Â Â Â TargetTriple(TT), FrameLowering(),<br>
-Â Â Â InstrInfo(initializeSubtargetDependencies(CPU, FS)), TSInfo(),<br>
-Â Â Â TLInfo(TM, *this) {}<br>
+Â Â Â TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),<br>
+Â Â Â TSInfo(), TLInfo(TM, *this) {}<br>
<br>
 bool WebAssemblySubtarget::enableAtomicExpand() const {<br>
  // If atomics are disabled, atomic ops are lowered instead of expanded<br>
<br>
diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp<br>
index 7ed05fd0331dc..5b90c67deae61 100644<br>
--- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp<br>
+++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp<br>
@@ -80,9 +80,9 @@ namespace {<br>
   bool NegateIndex = false;<br>
<br>
   X86ISelAddressMode()<br>
-Â Â Â Â : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),<br>
-Â Â Â Â Â Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),<br>
-Â Â Â Â Â MCSym(nullptr), JT(-1), SymbolFlags(X86II::MO_NO_FLAG) {}<br>
+Â Â Â Â : BaseType(RegBase), Base_FrameIndex(0), Scale(1), Disp(0), GV(nullptr),<br>
+Â Â Â Â Â CP(nullptr), BlockAddr(nullptr), ES(nullptr), MCSym(nullptr), JT(-1),<br>
+Â Â Â Â Â SymbolFlags(X86II::MO_NO_FLAG) {}<br>
<br>
   bool hasSymbolicDisplacement() const {<br>
    return GV != nullptr || CP != nullptr || ES != nullptr ||<br>
<br>
diff --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp<br>
index 8abbaa92c8cf6..28d57ca9ae3c7 100644<br>
--- a/llvm/lib/Target/X86/X86InstructionSelector.cpp<br>
+++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp<br>
@@ -153,8 +153,8 @@ class X86InstructionSelector : public InstructionSelector {<br>
 X86InstructionSelector::X86InstructionSelector(const X86TargetMachine &TM,<br>
                        const X86Subtarget &STI,<br>
                        const X86RegisterBankInfo &RBI)<br>
-Â Â : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()),<br>
-Â Â Â TRI(*STI.getRegisterInfo()), RBI(RBI),<br>
+Â Â : TM(TM), STI(STI), TII(*STI.getInstrInfo()), TRI(*STI.getRegisterInfo()),<br>
+Â Â Â RBI(RBI),<br>
 #define GET_GLOBALISEL_PREDICATES_INIT<br>
 #include "X86GenGlobalISel.inc"<br>
 #undef GET_GLOBALISEL_PREDICATES_INIT<br>
<br>
diff --git a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp<br>
index 9c076d2d67694..497a8f6e065fd 100644<br>
--- a/llvm/lib/Target/X86/X86RegisterBankInfo.cpp<br>
+++ b/llvm/lib/Target/X86/X86RegisterBankInfo.cpp<br>
@@ -25,8 +25,7 @@ using namespace llvm;<br>
 #define GET_TARGET_REGBANK_INFO_IMPL<br>
 #include "X86GenRegisterBankInfo.def"<br>
<br>
-X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI)<br>
-Â Â : X86GenRegisterBankInfo() {<br>
+X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI) {<br>
<br>
  // validate RegBank initialization.<br>
  const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID);<br>
<br>
diff --git a/llvm/lib/Target/XCore/XCoreSubtarget.cpp b/llvm/lib/Target/XCore/XCoreSubtarget.cpp<br>
index 1be707cb488cb..051d51178baa4 100644<br>
--- a/llvm/lib/Target/XCore/XCoreSubtarget.cpp<br>
+++ b/llvm/lib/Target/XCore/XCoreSubtarget.cpp<br>
@@ -26,5 +26,5 @@ void XCoreSubtarget::anchor() { }<br>
<br>
 XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU,<br>
                const std::string &FS, const TargetMachine &TM)<br>
-Â Â : XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), InstrInfo(),<br>
-Â Â Â FrameLowering(*this), TLInfo(TM, *this), TSInfo() {}<br>
+Â Â : XCoreGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), FrameLowering(*this),<br>
+Â Â Â TLInfo(TM, *this), TSInfo() {}<br>
<br>
diff --git a/llvm/lib/Transforms/IPO/Inliner.cpp b/llvm/lib/Transforms/IPO/Inliner.cpp<br>
index 4e3689f095363..0fef01a47b04b 100644<br>
--- a/llvm/lib/Transforms/IPO/Inliner.cpp<br>
+++ b/llvm/lib/Transforms/IPO/Inliner.cpp<br>
@@ -1073,8 +1073,7 @@ ModuleInlinerWrapperPass::ModuleInlinerWrapperPass(InlineParams Params,<br>
                          bool MandatoryFirst,<br>
                          InliningAdvisorMode Mode,<br>
                          unsigned MaxDevirtIterations)<br>
-Â Â : Params(Params), Mode(Mode), MaxDevirtIterations(MaxDevirtIterations),<br>
-Â Â Â PM(), MPM() {<br>
+Â Â : Params(Params), Mode(Mode), MaxDevirtIterations(MaxDevirtIterations) {<br>
  // Run the inliner first. The theory is that we are walking bottom-up and so<br>
  // the callees have already been fully optimized, and we want to inline them<br>
  // into the callers so that our optimizations can reflect that.<br>
<br>
diff --git a/llvm/lib/Transforms/IPO/PartialInlining.cpp b/llvm/lib/Transforms/IPO/PartialInlining.cpp<br>
index 2d717475ce7f1..fe9586ce75a62 100644<br>
--- a/llvm/lib/Transforms/IPO/PartialInlining.cpp<br>
+++ b/llvm/lib/Transforms/IPO/PartialInlining.cpp<br>
@@ -169,8 +169,7 @@ struct FunctionOutliningInfo {<br>
 };<br>
<br>
 struct FunctionOutliningMultiRegionInfo {<br>
-Â FunctionOutliningMultiRegionInfo()<br>
-Â Â Â : ORI() {}<br>
+Â FunctionOutliningMultiRegionInfo() {}<br>
<br>
  // Container for outline regions<br>
  struct OutlineRegionInfo {<br>
<br>
diff --git a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp<br>
index 73f208abcb07a..e9c4a56a90c2e 100644<br>
--- a/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp<br>
+++ b/llvm/lib/Transforms/Instrumentation/InstrProfiling.cpp<br>
@@ -248,8 +248,7 @@ class PGOCounterPromoter {<br>
  PGOCounterPromoter(<br>
    DenseMap<Loop *, SmallVector<LoadStorePair, 8>> &LoopToCands,<br>
    Loop &CurLoop, LoopInfo &LI, BlockFrequencyInfo *BFI)<br>
-Â Â Â : LoopToCandidates(LoopToCands), ExitBlocks(), InsertPts(), L(CurLoop),<br>
-Â Â Â Â LI(LI), BFI(BFI) {<br>
+Â Â Â : LoopToCandidates(LoopToCands), L(CurLoop), LI(LI), BFI(BFI) {<br>
<br>
   // Skip collection of ExitBlocks and InsertPts for loops that will not be<br>
   // able to have counters promoted.<br>
<br>
diff --git a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp<br>
index 4e4097e13271b..accaa1088d6fd 100644<br>
--- a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp<br>
+++ b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp<br>
@@ -220,9 +220,7 @@ class LowerMatrixIntrinsics {<br>
   bool IsColumnMajor = true;<br>
<br>
  public:<br>
-Â Â MatrixTy()<br>
-Â Â Â Â : Vectors(),<br>
-Â Â Â Â Â IsColumnMajor(MatrixLayout == MatrixLayoutTy::ColumnMajor) {}<br>
+Â Â MatrixTy() : IsColumnMajor(MatrixLayout == MatrixLayoutTy::ColumnMajor) {}<br>
   MatrixTy(ArrayRef<Value *> Vectors)<br>
     : Vectors(Vectors.begin(), Vectors.end()),<br>
      IsColumnMajor(MatrixLayout == MatrixLayoutTy::ColumnMajor) {}<br>
@@ -1832,7 +1830,7 @@ class LowerMatrixIntrinsics {<br>
          const DenseMap<Value *, SmallPtrSet<Value *, 2>> &Shared,<br>
          const SmallSetVector<Value *, 32> &ExprsInSubprogram,<br>
          Value *Leaf)<br>
-Â Â Â Â : Str(), Stream(Str), DL(DL), Inst2Matrix(Inst2Matrix), Shared(Shared),<br>
+Â Â Â Â : Stream(Str), DL(DL), Inst2Matrix(Inst2Matrix), Shared(Shared),<br>
      ExprsInSubprogram(ExprsInSubprogram), Leaf(Leaf) {}<br>
<br>
   void indent(unsigned N) {<br>
<br>
diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h<br>
index a8102c0b07b88..503cb1123e4e5 100644<br>
--- a/llvm/lib/Transforms/Vectorize/VPlan.h<br>
+++ b/llvm/lib/Transforms/Vectorize/VPlan.h<br>
@@ -198,8 +198,8 @@ struct VPTransformState {<br>
  VPTransformState(ElementCount VF, unsigned UF, LoopInfo *LI,<br>
          DominatorTree *DT, IRBuilder<> &Builder,<br>
          InnerLoopVectorizer *ILV, VPlan *Plan)<br>
-Â Â Â : VF(VF), UF(UF), Instance(), LI(LI), DT(DT), Builder(Builder), ILV(ILV),<br>
-Â Â Â Â Plan(Plan) {}<br>
+Â Â Â : VF(VF), UF(UF), LI(LI), DT(DT), Builder(Builder), ILV(ILV), Plan(Plan) {<br>
+Â }<br>
<br>
  /// The chosen Vectorization and Unroll Factors of the loop being vectorized.<br>
  ElementCount VF;<br>
<br>
diff --git a/llvm/tools/dsymutil/BinaryHolder.h b/llvm/tools/dsymutil/BinaryHolder.h<br>
index 5e81fe4b93b14..6245e49247337 100644<br>
--- a/llvm/tools/dsymutil/BinaryHolder.h<br>
+++ b/llvm/tools/dsymutil/BinaryHolder.h<br>
@@ -103,7 +103,7 @@ class BinaryHolder {<br>
    std::string Filename;<br>
    TimestampTy Timestamp;<br>
<br>
-Â Â Â KeyTy() : Filename(), Timestamp() {}<br>
+Â Â Â KeyTy() {}<br>
    KeyTy(StringRef Filename, TimestampTy Timestamp)<br>
      : Filename(Filename.str()), Timestamp(Timestamp) {}<br>
   };<br>
<br>
diff --git a/llvm/tools/dsymutil/Reproducer.cpp b/llvm/tools/dsymutil/Reproducer.cpp<br>
index 5c60758c6f80e..4f2e0db297e5c 100644<br>
--- a/llvm/tools/dsymutil/Reproducer.cpp<br>
+++ b/llvm/tools/dsymutil/Reproducer.cpp<br>
@@ -27,7 +27,7 @@ Reproducer::Reproducer() : VFS(vfs::getRealFileSystem()) {}<br>
 Reproducer::~Reproducer() = default;<br>
<br>
 ReproducerGenerate::ReproducerGenerate(std::error_code &EC)<br>
-Â Â : Root(createReproducerDir(EC)), FC() {<br>
+Â Â : Root(createReproducerDir(EC)) {<br>
  if (!Root.empty())<br>
   FC = std::make_shared<FileCollector>(Root, Root);<br>
  VFS = FileCollector::createCollectorVFS(vfs::getRealFileSystem(), FC);<br>
<br>
diff --git a/llvm/tools/llvm-cov/CoverageSummaryInfo.h b/llvm/tools/llvm-cov/CoverageSummaryInfo.h<br>
index 62e7cad1012b1..84a3228f22b9a 100644<br>
--- a/llvm/tools/llvm-cov/CoverageSummaryInfo.h<br>
+++ b/llvm/tools/llvm-cov/CoverageSummaryInfo.h<br>
@@ -191,8 +191,7 @@ struct FunctionCoverageSummary {<br>
  BranchCoverageInfo BranchCoverage;<br>
<br>
  FunctionCoverageSummary(const std::string &Name)<br>
-Â Â Â : Name(Name), ExecutionCount(0), RegionCoverage(), LineCoverage(),<br>
-Â Â Â Â BranchCoverage() {}<br>
+Â Â Â : Name(Name), ExecutionCount(0) {}<br>
<br>
  FunctionCoverageSummary(const std::string &Name, uint64_t ExecutionCount,<br>
              const RegionCoverageInfo &RegionCoverage,<br>
@@ -223,9 +222,7 @@ struct FileCoverageSummary {<br>
  FunctionCoverageInfo FunctionCoverage;<br>
  FunctionCoverageInfo InstantiationCoverage;<br>
<br>
-Â FileCoverageSummary(StringRef Name)<br>
-Â Â Â : Name(Name), RegionCoverage(), LineCoverage(), FunctionCoverage(),<br>
-Â Â Â Â InstantiationCoverage() {}<br>
+Â FileCoverageSummary(StringRef Name) : Name(Name) {}<br>
<br>
  FileCoverageSummary &operator+=(const FileCoverageSummary &RHS) {<br>
   RegionCoverage += RHS.RegionCoverage;<br>
<br>
diff --git a/llvm/tools/llvm-mca/CodeRegion.h b/llvm/tools/llvm-mca/CodeRegion.h<br>
index 0b2590767dfab..0e1e02a533d80 100644<br>
--- a/llvm/tools/llvm-mca/CodeRegion.h<br>
+++ b/llvm/tools/llvm-mca/CodeRegion.h<br>
@@ -63,7 +63,7 @@ class CodeRegion {<br>
<br>
 public:<br>
  CodeRegion(llvm::StringRef Desc, llvm::SMLoc Start)<br>
-Â Â Â : Description(Desc), RangeStart(Start), RangeEnd() {}<br>
+Â Â Â : Description(Desc), RangeStart(Start) {}<br>
<br>
  void addInstruction(const llvm::MCInst &Instruction) {<br>
   Instructions.emplace_back(Instruction);<br>
<br>
diff --git a/llvm/tools/llvm-mca/PipelinePrinter.h b/llvm/tools/llvm-mca/PipelinePrinter.h<br>
index fd262f0a8a5d5..d89e913f979f6 100644<br>
--- a/llvm/tools/llvm-mca/PipelinePrinter.h<br>
+++ b/llvm/tools/llvm-mca/PipelinePrinter.h<br>
@@ -53,7 +53,7 @@ class PipelinePrinter {<br>
 public:<br>
  PipelinePrinter(Pipeline &Pipe, const CodeRegion &R, unsigned Idx,<br>
          const MCSubtargetInfo &STI, const PipelineOptions &PO)<br>
-Â Â Â : P(Pipe), Region(R), RegionIdx(Idx), STI(STI), PO(PO), Views() {}<br>
+Â Â Â : P(Pipe), Region(R), RegionIdx(Idx), STI(STI), PO(PO) {}<br>
<br>
  void addView(std::unique_ptr<View> V) {<br>
   P.addEventListener(V.get());<br>
<br>
diff --git a/llvm/tools/llvm-objcopy/ELF/Object.h b/llvm/tools/llvm-objcopy/ELF/Object.h<br>
index 439380fc725b3..681ab8f56381c 100644<br>
--- a/llvm/tools/llvm-objcopy/ELF/Object.h<br>
+++ b/llvm/tools/llvm-objcopy/ELF/Object.h<br>
@@ -934,8 +934,7 @@ class BinaryELFBuilder : public BasicELFBuilder {<br>
<br>
 public:<br>
  BinaryELFBuilder(MemoryBuffer *MB, uint8_t NewSymbolVisibility)<br>
-Â Â Â : BasicELFBuilder(), MemBuf(MB),<br>
-Â Â Â Â NewSymbolVisibility(NewSymbolVisibility) {}<br>
+Â Â Â : MemBuf(MB), NewSymbolVisibility(NewSymbolVisibility) {}<br>
<br>
  Expected<std::unique_ptr<Object>> build();<br>
 };<br>
@@ -946,8 +945,7 @@ class IHexELFBuilder : public BasicELFBuilder {<br>
  void addDataSections();<br>
<br>
 public:<br>
-Â IHexELFBuilder(const std::vector<IHexRecord> &Records)<br>
-Â Â Â : BasicELFBuilder(), Records(Records) {}<br>
+Â IHexELFBuilder(const std::vector<IHexRecord> &Records) : Records(Records) {}<br>
<br>
  Expected<std::unique_ptr<Object>> build();<br>
 };<br>
<br>
diff --git a/llvm/tools/llvm-objdump/SourcePrinter.h b/llvm/tools/llvm-objdump/SourcePrinter.h<br>
index 21d5bdcf8a49d..31d46e3108f68 100644<br>
--- a/llvm/tools/llvm-objdump/SourcePrinter.h<br>
+++ b/llvm/tools/llvm-objdump/SourcePrinter.h<br>
@@ -80,7 +80,7 @@ class LiveVariablePrinter {<br>
<br>
 public:<br>
  LiveVariablePrinter(const MCRegisterInfo &MRI, const MCSubtargetInfo &STI)<br>
-Â Â Â : LiveVariables(), ActiveCols(Column()), MRI(MRI), STI(STI) {}<br>
+Â Â Â : ActiveCols(Column()), MRI(MRI), STI(STI) {}<br>
<br>
  void dump() const;<br>
<br>
<br>
diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp<br>
index 6c12750a9ddf1..0d7eabd6d1584 100644<br>
--- a/llvm/tools/llvm-profdata/llvm-profdata.cpp<br>
+++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp<br>
@@ -204,8 +204,8 @@ struct WriterContext {<br>
<br>
  WriterContext(bool IsSparse, std::mutex &ErrLock,<br>
         SmallSet<instrprof_error, 4> &WriterErrorCodes)<br>
-Â Â Â : Lock(), Writer(IsSparse), Errors(), ErrLock(ErrLock),<br>
-Â Â Â Â WriterErrorCodes(WriterErrorCodes) {}<br>
+Â Â Â : Writer(IsSparse), ErrLock(ErrLock), WriterErrorCodes(WriterErrorCodes) {<br>
+Â }<br>
 };<br>
<br>
 /// Computer the overlap b/w profile BaseFilename and TestFileName,<br>
@@ -2303,8 +2303,7 @@ struct HotFuncInfo {<br>
  uint64_t EntryCount;<br>
<br>
  HotFuncInfo()<br>
-Â Â Â : FuncName(), TotalCount(0), TotalCountPercent(0.0f), MaxCount(0),<br>
-Â Â Â Â EntryCount(0) {}<br>
+Â Â Â : TotalCount(0), TotalCountPercent(0.0f), MaxCount(0), EntryCount(0) {}<br>
<br>
  HotFuncInfo(StringRef FN, uint64_t TS, double TSP, uint64_t MS, uint64_t ES)<br>
    : FuncName(FN.begin(), FN.end()), TotalCount(TS), TotalCountPercent(TSP),<br>
<br>
diff --git a/llvm/tools/llvm-readobj/llvm-readobj.cpp b/llvm/tools/llvm-readobj/llvm-readobj.cpp<br>
index 46862bbad7cb6..eea486abe0a10 100644<br>
--- a/llvm/tools/llvm-readobj/llvm-readobj.cpp<br>
+++ b/llvm/tools/llvm-readobj/llvm-readobj.cpp<br>
@@ -286,8 +286,8 @@ static void parseOptions(const opt::InputArgList &Args) {<br>
 namespace {<br>
 struct ReadObjTypeTableBuilder {<br>
  ReadObjTypeTableBuilder()<br>
-Â Â Â : Allocator(), IDTable(Allocator), TypeTable(Allocator),<br>
-Â Â Â Â GlobalIDTable(Allocator), GlobalTypeTable(Allocator) {}<br>
+Â Â Â : IDTable(Allocator), TypeTable(Allocator), GlobalIDTable(Allocator),<br>
+Â Â Â Â GlobalTypeTable(Allocator) {}<br>
<br>
  llvm::BumpPtrAllocator Allocator;<br>
  llvm::codeview::MergingTypeTableBuilder IDTable;<br>
<br>
diff --git a/llvm/utils/TableGen/GlobalISel/GIMatchDag.h b/llvm/utils/TableGen/GlobalISel/GIMatchDag.h<br>
index 5675805408779..37570648cad17 100644<br>
--- a/llvm/utils/TableGen/GlobalISel/GIMatchDag.h<br>
+++ b/llvm/utils/TableGen/GlobalISel/GIMatchDag.h<br>
@@ -84,9 +84,7 @@ class GIMatchDag {<br>
  bool HasPostMatchPredicate = false;<br>
<br>
 public:<br>
-Â GIMatchDag(GIMatchDagContext &Ctx)<br>
-Â Â Â : Ctx(Ctx), InstrNodes(), PredicateNodes(), Edges(),<br>
-Â Â Â Â PredicateDependencies() {}<br>
+Â GIMatchDag(GIMatchDagContext &Ctx) : Ctx(Ctx) {}<br>
  GIMatchDag(const GIMatchDag &) = delete;<br>
<br>
  GIMatchDagContext &getContext() const { return Ctx; }<br>
<br>
diff --git a/llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp b/llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp<br>
index d08a83333c305..00d57404b0698 100644<br>
--- a/llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp<br>
+++ b/llvm/utils/TableGen/GlobalISel/GIMatchTree.cpp<br>
@@ -82,7 +82,6 @@ GIMatchTreeBuilderLeafInfo::GIMatchTreeBuilderLeafInfo(<br>
   GIMatchTreeBuilder &Builder, StringRef Name, unsigned RootIdx,<br>
   const GIMatchDag &MatchDag, void *Data)<br>
   : Builder(Builder), Info(Name, RootIdx, Data), MatchDag(MatchDag),<br>
-Â Â Â InstrNodeToInfo(),<br>
    RemainingInstrNodes(BitVector(MatchDag.getNumInstrNodes(), true)),<br>
    RemainingEdges(BitVector(MatchDag.getNumEdges(), true)),<br>
    RemainingPredicates(BitVector(MatchDag.getNumPredicates(), true)),<br>
<br>
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp<br>
index 7b1bd41a951bb..25bc0adc2a813 100644<br>
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp<br>
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp<br>
@@ -883,9 +883,7 @@ class RuleMatcher : public Matcher {<br>
<br>
 public:<br>
  RuleMatcher(ArrayRef<SMLoc> SrcLoc)<br>
-Â Â Â : Matchers(), Actions(), InsnVariableIDs(), MutatableInsns(),<br>
-Â Â Â Â DefinedOperands(), NextInsnVarID(0), NextOutputInsnID(0),<br>
-Â Â Â Â NextTempRegID(0), SrcLoc(SrcLoc), ComplexSubOperands(),<br>
+Â Â Â : NextInsnVarID(0), NextOutputInsnID(0), NextTempRegID(0), SrcLoc(SrcLoc),<br>
     RuleID(NextRuleID++) {}<br>
  RuleMatcher(RuleMatcher &&Other) = default;<br>
  RuleMatcher &operator=(RuleMatcher &&Other) = default;<br>
<br>
diff --git a/llvm/utils/TableGen/PredicateExpander.h b/llvm/utils/TableGen/PredicateExpander.h<br>
index 29cca92d902ce..9e7a4a3925acf 100644<br>
--- a/llvm/utils/TableGen/PredicateExpander.h<br>
+++ b/llvm/utils/TableGen/PredicateExpander.h<br>
@@ -111,7 +111,7 @@ class STIPredicateExpander : public PredicateExpander {<br>
<br>
 public:<br>
  STIPredicateExpander(StringRef Target)<br>
-Â Â Â : PredicateExpander(Target), ClassPrefix(), ExpandDefinition(false) {}<br>
+Â Â Â : PredicateExpander(Target), ExpandDefinition(false) {}<br>
<br>
  bool shouldExpandDefinition() const { return ExpandDefinition; }<br>
  StringRef getClassPrefix() const { return ClassPrefix; }<br>
<br>
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp<br>
index 0725657150f85..61f71309b6fb2 100644<br>
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp<br>
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp<br>
@@ -42,7 +42,7 @@ class RegisterBank {<br>
<br>
 public:<br>
  RegisterBank(const Record &TheDef)<br>
-Â Â Â : TheDef(TheDef), RCs(), RCWithLargestRegsSize(nullptr) {}<br>
+Â Â Â : TheDef(TheDef), RCWithLargestRegsSize(nullptr) {}<br>
<br>
  /// Get the human-readable name for the bank.<br>
  StringRef getName() const { return TheDef.getValueAsString("Name"); }<br>
<br>
<br>
<br>
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