[PATCH] D114405: Optimize shift and accumulate pattern in AArch64.

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Thanks. I like the added Known bits - they can be useful in many situations.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1808
+    APInt Mask = APInt::getMaxValue(Known.getBitWidth());
+    uint64_t Position = Known2.getConstant().getZExtValue();
+    uint64_t Shift = Known3.getConstant().getZExtValue();
----------------
We know that the operands 1 and 2 will be constants, so I think we can just grab the values for them directly:
```
uint64_t Mask = ~(Op->getConstantOperandVal(1) << Op->getConstantOperandVal(2));
```
The Mask then specifies which bits are known to be 0.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:8221
+// Treat an 'or' node is as an 'add' if the or'ed operands have no common bits.
+def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
+   return CurDAG->haveNoCommonBitsSet(N->getOperand(0), N->getOperand(1));
----------------
Now that we have this, it may be worth using it in the existing patterns, using a PatFrags that accepts either "add" or "or_is_add". That would save the need for new patterns.


================
Comment at: llvm/test/CodeGen/AArch64/shift-accumulate.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
----------------
Can you run the update_llc_test_checks on the file? It's missing some expected output.

It's also worth adding some simple case for each signedness / type that have tablegen patterns added / changed.


================
Comment at: llvm/test/CodeGen/AArch64/shift-accumulate.ll:18
+; CHECK-LABEL: ssra:
+; CHECK:  ssra    v0.8h, v1.8h, #14
+  ; Set the 15th bit to zero.
----------------
Unfortunately this doesn't verify. I think because the BIC code is giving incorrect Known bits.


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  https://reviews.llvm.org/D114405/new/

https://reviews.llvm.org/D114405